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11. 发明授权

US07171604B2 Method and apparatus for calculating cyclic redundancy check (CRC) on data using a programmable CRC engine 有权
标题翻译：使用可编程CRC引擎计算循环冗余校验（CRC）数据的方法和装置
公开(公告)号：US07171604B2
公开(公告)日：2007-01-30
申请号：US10749128
申请日：2003-12-30
申请人： Jaroslaw J. Sydir , Alok J Mathur , Wajdi Feghali , Kamal J. Koshy , Eduard Lecha
发明人： Jaroslaw J. Sydir , Alok J Mathur , Wajdi Feghali , Kamal J. Koshy , Eduard Lecha
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6516
摘要： Configurable CRC calculation engines and methods of performing CRC calculations are presented. The configurable CRC calculation engines calculate a CRC value for the data using an associated polynomial and remainder. The method includes receiving a polynomial, receiving a block of data to determine a CRC value for, and calculating a CRC value for the data using the polynomial. With such devices and methods, the configurable CRC calculation engines are useful in various applications and protocols.
摘要翻译：介绍了可配置的CRC计算引擎和执行CRC计算的方法。可配置CRC计算引擎使用相关联的多项式和余数来计算数据的CRC值。该方法包括接收多项式，接收数据块以确定CRC值，并使用多项式计算数据的CRC值。使用这种设备和方法，可配置CRC计算引擎在各种应用和协议中是有用的。

12. 发明授权

US07607068B2 Apparatus and method for generating a Galois-field syndrome 失效
标题翻译：用于产生伽罗瓦氏综合征的装置和方法
公开(公告)号：US07607068B2
公开(公告)日：2009-10-20
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

13. 发明申请

US20080159528A1 Method for Processing Multiple Operations 有权
标题翻译：多操作处理方法
公开(公告)号：US20080159528A1
公开(公告)日：2008-07-03
申请号：US11617418
申请日：2006-12-28
申请人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
发明人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
IPC分类号： H04L9/30 , H04L9/28
CPC分类号： H04L63/0485 , G06F9/30181 , G06F9/3879 , H04L63/08
摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

14. 发明申请

US20080148011A1 Carry/Borrow Handling 审中-公开
标题翻译：携带/借款处理
公开(公告)号：US20080148011A1
公开(公告)日：2008-06-19
申请号：US11610897
申请日：2006-12-14
申请人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
发明人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
IPC分类号： G06F9/30
CPC分类号： G06F9/3001
摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了用于执行进位/借用处理的系统和方法。根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

15. 发明申请

US20080144811A1 Method for Simultaneous Modular Exponentiations 有权
标题翻译：同时模块化指标的方法
公开(公告)号：US20080144811A1
公开(公告)日：2008-06-19
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

16. 发明申请

US20080075278A1 TECHNIQUES FOR MERGING TABLES 失效
标题翻译：合并表的技术
公开(公告)号：US20080075278A1
公开(公告)日：2008-03-27
申请号：US11534330
申请日：2006-09-22
申请人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
发明人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
IPC分类号： H04L9/30
CPC分类号： H04L9/0618 , G09C1/00 , H04L2209/122
摘要： Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.
摘要翻译：这里描述了覆盖和合并任意数目的等效大小和结构的表的技术。可以将表中相似的比特或模式设置为表示相应的逻辑“0”或“1”的电压值。表中不同的位可以连接到表选择信号的值或其反相。

17. 发明授权

US07801299B2 Techniques for merging tables 失效
标题翻译：合并表格的技巧
公开(公告)号：US07801299B2
公开(公告)日：2010-09-21
申请号：US11534330
申请日：2006-09-22
申请人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
发明人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
IPC分类号： H04L9/30
CPC分类号： H04L9/0618 , G09C1/00 , H04L2209/122
摘要： Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.
摘要翻译：这里描述了覆盖和合并任意数目的等效大小和结构的表的技术。可以将表中相似的比特或模式设置为表示相应的逻辑“0”或“1”的电压值。表中不同的位可以连接到表选择信号的值或其反相。

18. 发明申请

US20080162806A1 Storage Accelerator 有权
标题翻译：存储加速器
公开(公告)号：US20080162806A1
公开(公告)日：2008-07-03
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G06F12/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

19. 发明申请

US20080148024A1 Hardware Accelerator 有权
标题翻译：硬件加速器
公开(公告)号：US20080148024A1
公开(公告)日：2008-06-19
申请号：US11610871
申请日：2006-12-14
申请人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F21/72
摘要： The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于指令处理的方法。该方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位。该方法还可以包括将和加载到第三寄存器中，并且将进位位加载到第三寄存器的最高有效位位置以产生第三操作数。该方法还可以包括经由移位器单元在第三操作数上执行单位移位以产生移位的操作数，并将移位的操作数加载到第四寄存器中。该方法还可以包括将最小有效位加载到第四寄存器的最高有效位位置以产生第四操作数。该方法可以另外包括经由第四操作数生成第一和第二操作数的最大公约数（GCD），并且至少部分地基于GCD生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

20. 发明申请

US20080140753A1 Multiplier 审中-公开
标题翻译：乘数
公开(公告)号：US20080140753A1
公开(公告)日：2008-06-12
申请号：US11636016
申请日：2006-12-08
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G06F17/00
CPC分类号： G06F7/5324
摘要： An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1. The multiplying includes determining partial product values for at least some of aibj and determining a sum of partial product values for aibj and ajbi where ai=bj and bj=ai for respective values of i and j, by multiplying one of (1) aibj and (2) ajbi by two. A sum is determined and stored in a memory storage element of the determined partial product values and the determined sum of partial product values for aibj and ajbi.
摘要翻译：电子实现的方法包括将数字A和数字B相乘，其中A由段α1和B组成，并且B由分段b和j分别组成，其中i和j是大于1的整数。乘法包括确定对于第一个子集的至少一些的部分乘积值，并且确定第一个子集的部分乘积值的和， / SUB＆gt; j＆lt; i＆gt;和＆lt; i＆lt; i＆lt; i＆lt; i＆lt; i＆lt; 并且对于i和j的各个值，通过将（1）a个子集合中的一个来代替，并且对于i和j的各个值，b＆lt; i＆lt; i＆lt; 和（2）第二个和第二个。确定和并将其存储在所确定的部分乘积值的存储器存储元件中，并且将所确定的部分乘积值的总和存储到第一和第二 b

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