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11. 发明授权

US06925005B2 AC sensing method memory circuit 失效
标题翻译：交流感测方式存储电路
公开(公告)号：US06925005B2
公开(公告)日：2005-08-02
申请号：US10647441
申请日：2003-08-26
申请人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
发明人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
IPC分类号： G11C16/06 , G11C5/00 , G11C16/04 , G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3436
摘要： The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.
摘要翻译：本发明是一种存储器电路，包括：存储单元阵列，包括多个位线，多个字线以及设置在位线和字线之间的交叉位置的多个存储单元; 以及页缓冲器，其连接到位线，并且通过根据所选择的存储器的单元电流在预充电位线电位被放电时，用预定的感测定时判断位线的电位来检测存储单元数据细胞。此外，感测定时根据存储单元阵列中所选存储单元的位置而不同。

12. 发明授权

US06739034B2 Assembling apparatus for electrical machine having permanently magnetized field magnets 失效
标题翻译：具有永磁磁场的电机组装装置
公开(公告)号：US06739034B2
公开(公告)日：2004-05-25
申请号：US09800709
申请日：2001-03-07
申请人： Akira Suzuki , Kenji Nagai , Hiroaki Kondo
发明人： Akira Suzuki , Kenji Nagai , Hiroaki Kondo
IPC分类号： H02K1500
CPC分类号： B23P19/00 , H02K15/03 , H02K15/16 , Y10T29/49009 , Y10T29/49012 , Y10T29/49904 , Y10T29/53143 , Y10T29/53161
摘要： An assembling apparatus for assembling rotating electrical machines having permanent magnets and armatures cores. The apparatus holds the armature core while the permanent magnets are assembled on to it thus avoiding hand labor. At all times, the rotor is supported so that it cannot cant relative to the stator and its permanent magnets and thus, no damage to the magnets or any coating thereon or to the armature will occur.
摘要翻译：一种用于组装具有永磁体和电枢芯的旋转电机的组装装置。该装置保持电枢铁心，而永磁体组装在其上，从而避免手工劳动。在任何时候，转子被支撑成使得其不能相对于定子及其永久磁体倾斜，因此不会对磁体或其上的任何涂层或电枢产生损害。

13. 发明授权

US06686750B2 Semiconductor integrated circuit device and IC card 有权
标题翻译：半导体集成电路器件和IC卡
公开(公告)号：US06686750B2
公开(公告)日：2004-02-03
申请号：US10164641
申请日：2002-06-10
申请人： Kazuki Watanabe , Ryouzou Yoshino , Kenji Nagai , Tatsuya Nishihara
发明人： Kazuki Watanabe , Ryouzou Yoshino , Kenji Nagai , Tatsuya Nishihara
IPC分类号： G01R2708
CPC分类号： G06K19/0716 , G06K19/073 , G06K19/07728 , H01L27/0802
摘要： A semiconductor integrated circuit device is provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area in which one wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.
摘要翻译：半导体集成电路器件设置有IC芯片，以防止IC芯片破裂时其电路发生故障。为了检测芯片裂纹，电阻器R01设置在想要检测芯片裂纹的区域的外周。如果芯片破裂并且电阻器R01的电阻值改变，则检测电阻变化，从而控制诸如上电复位信号的内部信号，并停止电路装置的整个操作，以防止电路故障。因此，系统安全性也可以提高。

14. 发明授权

US06427065B1 Power transmission system, IC card and information communication system using IC card 失效
标题翻译：电力传输系统，IC卡和使用IC卡的信息通信系统
公开(公告)号：US06427065B1
公开(公告)日：2002-07-30
申请号：US09639070
申请日：2000-08-16
申请人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
发明人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
IPC分类号： H04B500
CPC分类号： G06K19/0726 , G06K7/0008 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G07C9/00111 , H01Q1/22 , H01Q1/2225 , H01Q7/005 , H02J17/00 , H02J50/12 , H02J50/90
摘要： The present invention comprises a power transmission system, an IC card, and an information communication system using an IC card. In the power transmission system, power is transmitted by radio from the power transmission device to the IC card. In the IC card, the transmitted induced power is converted into a DC voltage, the transmitted induced power or a voltage corresponding to the induced power is detected, and a desired DC voltage to be suppled to the internal circuit is obtained in controlling resistance the detected induced power or the voltage corresponding to the induced power.
摘要翻译：本发明包括电力传输系统，IC卡和使用IC卡的信息通信系统。在电力传输系统中，通过无线电从电力传输装置向IC卡发送电力。在IC卡中，所传输的感应功率被转换为直流电压，检测所传输的感应功率或与感应功率相对应的电压，并且在控制检测到的电阻时获得要提供给内部电路的期望直流电压感应功率或对应于感应功率的电压。

15. 发明授权

US5619465A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5619465A
公开(公告)日：1997-04-08
申请号：US584471
申请日：1996-01-11
申请人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
发明人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
IPC分类号： G11C7/06 , G11C11/406 , G11C11/4091 , G11C7/02
CPC分类号： G11C11/406 , G11C11/4091 , G11C7/065
摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.
摘要翻译：公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

16. 发明授权

US4562408A Amplifier having a high power source noise repression ratio 失效
标题翻译：具有高电源噪声抑制比的放大器
公开(公告)号：US4562408A
公开(公告)日：1985-12-31
申请号：US560873
申请日：1983-12-13
申请人： Kenji Nagai , Fumiaki Fujii
发明人： Kenji Nagai , Fumiaki Fujii
IPC分类号： H03F3/345 , H03F1/08 , H03F3/30 , H03F3/34 , H03F3/45 , H03F3/16
CPC分类号： H03F3/45188 , H03F1/086 , H03F3/3023 , H03F2200/153 , H03F2203/45398 , H03F2203/45508 , H03F2203/45631
摘要： An amplifier comprising a pair of differential input MISFETs, a current mirror circuit connected between the drains of the differential input MISFETs and a power source terminal, a phase compensation circuit connected to the drain of one of the differential input MISFETs, an output stage amplification circuit amplifying the signal produced at the drain of one of the differential input MISFETs, a phase regulation circuit such as a capacitor connected to the other of the differential input transistors, and a feedback circuit feeding back the output signal produced from the output stage amplification circuit to the other of the differential input MISFETs in order to apply negative feedback to the amplifier. Since the capacitor is provided, the phase of the power source noise can be made substantially equal to the phase of noise occurring at the drain of one of the differential input MISFETs due to the power source noise. Hence, hardly any noise is produced from the output stage amplification circuit. Since feedback is applied to the amplifier, the noise occurring at the drain of the other of the differential input MISFETs operates in such a manner as to limit the amount of change of the drain voltage of one of the differential input MISFETs due to the noise. As a result, a large change of the output signal due to the power source noise can be prevented. Furthermore, since an element to be added for this purpose may be merely a capacitor, a significant increase in the number of circuit elements can be avoided.
摘要翻译：一种放大器，包括一对差分输入MISFET，连接在差分输入MISFET的漏极和电源端子之间的电流镜电路，连接到差分输入MISFET之一的漏极的相位补偿电路，输出级放大电路放大在差分输入MISFET中的一个的漏极产生的信号，连接到另一个差分输入晶体管的电容器等电容器，以及将由输出级放大电路产生的输出信号反馈到另一个差分输入MISFET，以便向放大器施加负反馈。由于提供了电容器，所以可以使电源噪声的相位基本上等于由于电源噪声而在差分输入MISFET之一的漏极处产生的噪声的相位。因此，几乎不会从输出级放大电路产生任何噪声。由于反馈被应用于放大器，所以在另一个差分输入MISFET的漏极处发生的噪声以限制由噪声引起的差动输入MISFET之一的漏极电压的变化量的方式工作。结果，可以防止由于电源噪声引起的输出信号的大的变化。此外，由于为此目的添加的元件可以仅仅是电容器，所以可以避免电路元件的数量的显着增加。

17. 发明授权

US07738143B2 Copy-forgery-inhibited pattern or stamp image combined with image data based on user actions 失效
标题翻译：基于用户动作与图像数据组合的防伪图案或印记图像
公开(公告)号：US07738143B2
公开(公告)日：2010-06-15
申请号：US11610660
申请日：2006-12-14
申请人： Koichi Ishimoto , Masaki Kashiwagi , Nobuaki Miyahara , Takayuki Hirata , Yousuke Aoki , Asami Horiuchi , Kenji Nagai , Shuuko Kikuchi
发明人： Koichi Ishimoto , Masaki Kashiwagi , Nobuaki Miyahara , Takayuki Hirata , Yousuke Aoki , Asami Horiuchi , Kenji Nagai , Shuuko Kikuchi
IPC分类号： H04N1/00 , H04N1/387 , B41M3/14
CPC分类号： G03G21/043 , H04N1/00838 , H04N1/00883
摘要： The image data with the copy-forgery-inhibited pattern image added and an image area flag signal stored in the hard disk drive are inputted into a thinning filter. A thinning circuit does not perform thinning processing on these pieces of data and outputs the inputted image, as it is. The filter performs processing so that an image of a copy-forgery-inhibited pattern background part may be deleted. A selector selects an image signal not passing through the filter for a latent mark of the copy-forgery-inhibited pattern whose image area flag is set as “Character,” and select an image signal subjected to the processing by the filter for a copy-forgery-inhibited pattern background part whose image area flag is set as “Photograph.” By doing so, it is possible to perform low pass processing on only the copy-forgery-inhibited pattern background part and perform processing of making a latent-mark part emerge.
摘要翻译：添加了禁止复制伪造图案的图像数据和存储在硬盘驱动器中的图像区域标志信号被输入到稀疏滤波器中。稀疏电路不对这些数据进行稀疏化处理，直接输出输入的图像。过滤器执行处理，使得可以删除禁止复印伪造图案的图像的图像。选择器将图像区域标志设置为“字符”的复制防伪图案的潜在标记选择未通过滤光器的图像信号，并选择由滤色器进行处理的图像信号，其图像区域标记被设置为“照片”的伪造抑制图案背景部分。通过这样做，可以仅对禁止伪造的图案背景部分执行低通处理，并且执行使潜像标记部分出现。

18. 发明授权

US07706197B2 Storage device and control method of storage device 有权
标题翻译：存储设备的存储设备和控制方法
公开(公告)号：US07706197B2
公开(公告)日：2010-04-27
申请号：US11510077
申请日：2006-08-25
申请人： Kenji Nagai
发明人： Kenji Nagai
IPC分类号： G11C29/00 , G11C8/12
CPC分类号： G11C8/12
摘要： In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.
摘要翻译：在具有在多个块中划分的存储单元阵列的块单元中具有冗余补救功能的存储设备中，在对块内的各个存储单元的访问操作之前，输入用于指定块的块地址BA，并且块冗余在输入的块地址BA中确定，因此不需要在访问操作的每个场合确定块地址BA的输入或冗余。结果，可以缩短开始到存储单元的访问操作的时间，并且提高访问速度。

19. 发明申请

US20090323435A1 TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US20090323435A1
公开(公告)日：2009-12-31
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

20. 发明授权

US06385119B2 Internal supply voltage generating cicuit in a semiconductor memory device and method for controlling the same 有权
标题翻译：半导体存储器件中的内部电源电压生成电路及其控制方法
公开(公告)号：US06385119B2
公开(公告)日：2002-05-07
申请号：US09772076
申请日：2001-01-30
申请人： Isamu Kobayashi , Yoshiharu Kato , Kenji Nagai
发明人： Isamu Kobayashi , Yoshiharu Kato , Kenji Nagai
IPC分类号： G06F126
CPC分类号： G05F3/242
摘要： A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.
摘要翻译：用于控制内部电源电压发生电路的方法降低了活动模式下的功耗。内部电源电压产生电路包括向内部电路提供相对大的驱动功率的第一电压降调节器和向内部电路提供相对小的驱动功率的第二电压降调节器。首先，第二个电压降调节器被激活，第一个电压降调节器在待机模式和掉电模式之一被禁用。然后，至少第一电压降调节器在激活模式下被激活，并且第一电压降调节器在激活模式的活动暂停期间被非激活。当主动暂停被取消时，第一个电压降稳压器被激活。

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