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11. 发明授权

US09448964B2 Autonomous control in a programmable system 有权
标题翻译：可编程系统中的自主控制
公开(公告)号：US09448964B2
公开(公告)日：2016-09-20
申请号：US12765400
申请日：2010-04-22
申请人： Bert Sullam , Harold Kutz , Monte Mar , Eashwar Thiagaragen , Timothy Williams , David G. Wright
发明人： Bert Sullam , Harold Kutz , Monte Mar , Eashwar Thiagaragen , Timothy Williams , David G. Wright
IPC分类号： G06F15/177 , G06F15/78 , H04L25/03
CPC分类号： G05B19/042 , G05B2219/25257 , G06F15/7867 , H04L29/06 , H04L29/08981 , H04L2025/0342
摘要： A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously of the microcontroller.
摘要翻译：可编程系统包括可重构以执行各种模拟操作的可编程模拟系统，并且包括可重新配置以执行各种数字操作的可编程数字系统。可编程系统还包括能够重新配置和控制可编程模拟系统和可编程数字系统的微控制器。可编程数字系统被配置为自主地控制微控制器的可编程模拟系统。

12. 发明授权

US08601254B1 Configurable reset pin for input/output port 有权
标题翻译：可配置的输入/输出端口复位引脚
公开(公告)号：US08601254B1
公开(公告)日：2013-12-03
申请号：US12759426
申请日：2010-04-13
申请人： Harold Kutz , Timothy Williams , Bert Sullam , Robert W. Metzler , Craig Nemecek , Eric Blom , Melany Richmond , Warren Snyder , David G. Wright , Jeffrey Erickson , Greg Verge
发明人： Harold Kutz , Timothy Williams , Bert Sullam , Robert W. Metzler , Craig Nemecek , Eric Blom , Melany Richmond , Warren Snyder , David G. Wright , Jeffrey Erickson , Greg Verge
IPC分类号： G06F1/24 , H03K19/173
CPC分类号： G06F1/24 , H03K19/018585 , H03K19/018592 , H03K19/1732
摘要： A programmable system includes an input/output (I/O) pin that is configurable into multiple operational states. The programmable system further includes a memory device to store configuration data that, when provided to the I/O pin, causes the I/O pin to reconfigure into one of the operational states. When power is supplied to the system, the memory device is configured to provide the configuration data to the I/O pin prior to a system microcontroller becoming operational responsive to the power.
摘要翻译：可编程系统包括可配置为多种工作状态的输入/输出（I / O）引脚。可编程系统还包括存储器件，用于存储当提供给I / O引脚时使I / O引脚重新配置为其中一个操作状态的配置数据。当向系统供电时，存储器件被配置为在系统微控制器响应于电力而变得可操作之前将配置数据提供给I / O引脚。

13. 发明授权

US08299951B1 Clocking analog components operating in a digital system 有权
标题翻译：在数字系统中运行的时钟模拟组件
公开(公告)号：US08299951B1
公开(公告)日：2012-10-30
申请号：US13103862
申请日：2011-05-09
申请人： Harold Kutz , Timothy Williams
发明人： Harold Kutz , Timothy Williams
IPC分类号： H03M1/50
CPC分类号： H03M1/0818 , H03M1/12 , H03M1/66
摘要： A system and method are provided for operating first and second components in first and second domains. In one embodiment, the method includes: generating a plurality of clock signals shifted relative to one another; operating a first component in a first domain using a first one of the plurality of clock signals; operating a second component in a second domain using a second one of the plurality of clock signals selected using a selection component; and comparing a present output of the second component to a stored value, determining whether a variation between the present output and the stored value is greater than a threshold, and, if the variation is greater than the threshold, using a controller to cause the selection component to select a third clock signal from the plurality of clock signals that is shifted relative to the second clock signal to drive the second component.
摘要翻译：提供了用于在第一和第二域中操作第一和第二组件的系统和方法。在一个实施例中，该方法包括：产生相对于彼此移位的多个时钟信号; 使用所述多个时钟信号中的第一个来操作第一域中的第一分量; 使用使用选择部件选择的所述多个时钟信号中的第二个来操作第二域中的第二分量; 以及将所述第二分量的当前输出与存储值进行比较，确定所述当前输出和所述存储值之间的变化是否大于阈值，并且如果所述变化大于所述阈值，则使用控制器使所述选择从相对于第二时钟信号偏移的多个时钟信号中选择第三时钟信号以驱动第二分量。

14. 发明授权

US07940202B1 Clocking analog components operating in a digital system 有权
标题翻译：在数字系统中运行的时钟模拟组件
公开(公告)号：US07940202B1
公开(公告)日：2011-05-10
申请号：US12533772
申请日：2009-07-31
申请人： Harold Kutz , Timothy Williams
发明人： Harold Kutz , Timothy Williams
IPC分类号： H03M1/50
CPC分类号： H03M1/0818 , H03M1/12 , H03M1/66
摘要： In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.
摘要翻译：在一个示例中，时钟生成部件被配置为接收主时钟并且生成相对于彼此偏移的多个时钟信号，用于具有模拟域和数字域的芯片。第一选择部件被配置为选择所生成的时钟信号中的第一个，并根据第一时钟信号驱动数字域。第二选择部件被配置为选择相对于当前用于驱动数字域的驱动模拟域的模拟分量的第一时钟信号移位的生成的时钟信号中的第二选择部件。

15. 发明申请

US20110026519A1 DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP 有权
标题翻译：动态系统的动态可重构模拟路由电路及方法
公开(公告)号：US20110026519A1
公开(公告)日：2011-02-03
申请号：US12776323
申请日：2010-05-07
申请人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
发明人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , G06F2213/0038
摘要： An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.
摘要翻译：集成电路装置可以包括可重新配置的模拟信号交换结构，其包括响应于可变模拟路由数据而被引脚连接电路选择性地连接到外部引脚的多个全局总线，以及选择性地连接到模拟块的多个局部总线和/或全局总线，通过响应于模拟路由数据路由连接电路; 以及响应于指令数据执行预定操作的至少一个处理器电路。

16. 发明授权

US07089133B1 Method and circuit for providing a system level reset function for an electronic device 有权
标题翻译：为电子设备提供系统电平复位功能的方法和电路
公开(公告)号：US07089133B1
公开(公告)日：2006-08-08
申请号：US10942523
申请日：2004-09-15
申请人： Timothy Williams , Harold Kutz , Eric Blom , Warren Snyder
发明人： Timothy Williams , Harold Kutz , Eric Blom , Warren Snyder
IPC分类号： G06F19/00 , G06F1/24
CPC分类号： G06F1/24
摘要： A method and circuit provide a system level reset function for an electronic device. An initial reset function is provided under a low voltage condition of supply voltage, such as occur upon first energizing the electronic device. A tunable reset function is also provided, which can first be asserted at a voltage level setting less precise than that setting becomes upon tuning. Further, a boot-up reset function is provided, which provides its reset function at a voltage level setting that is set according to a calibration. Calibration can be based on data stored in a non-volatile memory, and can involve a checksum operation. The electronic device, a microcontroller for instance, is held in a reset state with any of the initial, tunable, and boot-up reset functions.
摘要翻译：方法和电路为电子设备提供系统级复位功能。在电源电压的低电压条件下提供初始复位功能，例如在电子设备首次通电时发生。还提供了可调谐复位功能，其可以首先在比调谐时设置的精度低的电压电平设置下被断言。此外，提供启动复位功能，其提供其按照校准设置的电压电平设置的复位功能。校准可以基于存储在非易失性存储器中的数据，并且可以涉及校验和操作。例如，电子设备（例如微控制器）被保持在具有任何初始，可调谐和启动复位功能的复位状态。

17. 发明授权

US09377905B1 Multiplexer for a TX/RX capacitance sensing panel 有权
标题翻译：用于TX / RX电容检测面板的多路复用器
公开(公告)号：US09377905B1
公开(公告)日：2016-06-28
申请号：US13360296
申请日：2012-01-27
申请人： Edward Grivna , Timothy Williams , Hans Klein
发明人： Edward Grivna , Timothy Williams , Hans Klein
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0416 , G06F2203/04111
摘要： An embodiment of a multiplexer circuit may include a plurality of PTOTAL receive (RX) channel outputs and a plurality of QTOTAL pins, where QTOTAL is greater than PTOTAL. Each of a first subset and a third subset of the plurality of QTOTAL pins may be switchably coupled to at least one of the plurality of RX channels, each of a second subset of the plurality of QTOTAL pins is switchably coupled to two of the plurality of RX channels, and for each possible subset of PTOTAL contiguous pins from the plurality of QTOTAL pins, each pin in the possible subset may be switchably coupled to a different RX channel output of the plurality of RX channel outputs.
摘要翻译：多路复用器电路的实施例可以包括多个PTOTAL接收（RX）信道输出和多个QTOTAL引脚，其中QTOTAL大于PTOTAL。多个QTOTAL引脚的第一子集和第三子集中的每一个可以可切换地耦合到多个RX信道中的至少一个，多个QTOTAL引脚的第二子集中的每一个可切换地耦合到多个 RX通道，并且对于来自多个QTOTAL引脚的PTOTAL连续引脚的每个可能子集，可能子集中的每个引脚可以可切换地耦合到多个RX通道输出的不同RX通道输出。

18. 发明申请

US20130284801A1 MOBILE COMMUNICATION TERMINAL CONFIGURED TO DISPLAY MULTI-SYMBOL DECODABLE INDICIA 有权
标题翻译：移动通信终端配置显示多符号可解译索引
公开(公告)号：US20130284801A1
公开(公告)日：2013-10-31
申请号：US13459833
申请日：2012-04-30
申请人： Timothy Meier , Timothy Williams , Stephen Patrick Deloge
发明人： Timothy Meier , Timothy Williams , Stephen Patrick Deloge
IPC分类号： G06K19/06 , G06F17/30
CPC分类号： H04M1/72522 , G06Q20/3274
摘要： A mobile communication terminal can comprise a housing, a microprocessor disposed within the housing, a display incorporated into the housing, and a communication interface communicatively coupled to the microprocessor. The mobile communication terminal can be configured, responsive to receiving a byte sequence representing a character string containing one or more alphanumeric or non-alphanumeric characters, to encode the byte sequence into one or more bar code symbols having a minimum dimension of a smallest element equaling or exceeding a readability threshold value. The mobile communication terminal can be further configured to display the bar code symbols.
摘要翻译：移动通信终端可以包括壳体，设置在壳体内的微处理器，并入壳体中的显示器以及通信地耦合到微处理器的通信接口。移动通信终端可以被配置为响应于接收到表示包含一个或多个字母数字或非字母数字字符的字符串的字节序列，以将该字节序列编码成一个或多个条形码符号，该条形码符号具有等于最小元素的最小尺寸或超过可读性阈值。移动通信终端还可以被配置为显示条形码符号。

19. 发明申请

US20130023815A1 SYSTEM AND METHOD FOR BIPHASIC TRANSDERMAL IONTOPHREOTIC DELIVERY OF THERAPEUTIC AGENTS 有权
公开(公告)号：US20130023815A1
公开(公告)日：2013-01-24
申请号：US13430662
申请日：2012-03-26
申请人： Mir Imran , Mir Hashim , Glen McLaughlin , Huma Arastu , Rekha Vaidyanathan , Joel Harris , Radhika Korupolu , Andrew Mangogna , Chang Ong , Sanjay Patel , Lu Wang , Timothy Williams
发明人： Mir Imran , Mir Hashim , Glen McLaughlin , Huma Arastu , Rekha Vaidyanathan , Joel Harris , Radhika Korupolu , Andrew Mangogna , Chang Ong , Sanjay Patel , Lu Wang , Timothy Williams
IPC分类号： A61N1/30
CPC分类号： A61N1/325 , A61K9/0009 , A61K9/0014 , A61K31/4178 , A61K31/4468 , A61K31/454 , A61K31/5415 , A61N1/0436 , A61N1/044 , A61N1/0448 , A61N1/30 , A61N1/303
摘要： Various embodiments provide methods and systems for the biphasic iontophoretic transdermal delivery of therapeutic agents. An embodiment of a method for such delivery comprises positioning at least one electrode assembly in electrical communication with a patient's skin. The assembly includes a solution comprising a therapeutic agent which passively diffuses into the skin. A dose of agent is delivered from the assembly into the skin during a first period using a first current having a characteristic e.g., polarity and magnitude, to repel the agent out of the assembly. During a second period, a second current having a characteristic to attract the agent is used to retain the agent in the assembly such that delivery of agent into skin is minimized. A dose of agent may be delivered on demand by an input from the patient. Embodiments may be used for delivery of agents which cause adverse effects from unwanted passive diffusion.

20. 发明申请

US20080263328A1 ORTHOGONAL REGISTER ACCESS 审中-公开
标题翻译：正交寄存器访问
公开(公告)号：US20080263328A1
公开(公告)日：2008-10-23
申请号：US11859547
申请日：2007-09-21
申请人： Timothy Williams , Gregory John Verge , Dennis Seguine
发明人： Timothy Williams , Gregory John Verge , Dennis Seguine
IPC分类号： G06F9/38
CPC分类号： G06F7/785
摘要： Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers.
摘要翻译：本发明的实施例涉及一种用于正交地访问一组并行寄存器的方法和系统。解码器可以用于选择并行寄存器集合的特定行或列，以对应于所选行的并行方式或对应于所选列的正交方式执行寄存器操作。因此，当选择特定行时，可以对所选择的行的每个位执行寄存器操作以产生并行寄存器输出，例如通过将所选择的行的每个位读/写到并行寄存器。另一方面，当选择特定列时，可以对所选列的每个位执行寄存器操作，例如通过将所选列的每个位读/写为正交寄存器。正交寄存器访问允许快速和有效地访问该并行寄存器集合中的特定位。

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