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11. 发明授权

US07439596B2 Transistors for semiconductor device and methods of fabricating the same 有权
标题翻译：用于半导体器件的晶体管及其制造方法
公开(公告)号：US07439596B2
公开(公告)日：2008-10-21
申请号：US11045060
申请日：2005-01-31
申请人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
发明人： Jae-Yoon Yoo , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee , Hyun-Suk Kim , Moon-Han Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66537 , H01L29/1083 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.
摘要翻译：本发明公开了一种用于半导体器件的晶体管，其能够防止由于杂质离子的扩散而产生栅极图案中的耗尽电容。本发明还公开了一种制造晶体管的方法。

12. 发明申请

US20080242010A1 At least penta-sided-channel type of finfet transistor 有权
标题翻译：至少五面通道型finfet晶体管
公开(公告)号：US20080242010A1
公开(公告)日：2008-10-02
申请号：US12149329
申请日：2008-04-30
申请人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
发明人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.
摘要翻译：至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

13. 发明申请

US20080036006A1 Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
标题翻译：具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US20080036006A1
公开(公告)日：2008-02-14
申请号：US11802281
申请日：2007-05-22
申请人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

14. 发明申请

US20070059606A1 Nonaqueous electrolyte for improving performance and litium secondary battery comprising the same 有权
标题翻译：用于改善性能的非水电解质和包含其的二次电池
公开(公告)号：US20070059606A1
公开(公告)日：2007-03-15
申请号：US11521892
申请日：2006-09-15
申请人： Ho Lee , Tae Park , Yong Choi , Soo Yoon , Hong Park , Hyun Jung , Jeong Ahn
发明人： Ho Lee , Tae Park , Yong Choi , Soo Yoon , Hong Park , Hyun Jung , Jeong Ahn
IPC分类号： H01M10/40
CPC分类号： H01M10/0567 , H01M4/131 , H01M4/139 , H01M10/04 , H01M10/052
摘要： Disclosed is a lithium secondary battery comprising a cathode, an anode, an electrolyte and a separator, wherein the anode comprises an anode active material having a specific surface area of 3 m2/g or less, and the electrolyte comprises 0.1˜6 parts by weight of a propane sultone-based compound based on 100 parts by weight of the electrolyte. The lithium secondary battery solves the problem of performance degradation caused by the use of an increased amount of a propane sultone-based compound required to form a SEI film on the surface of an anode upon the first charge cycle. Also, the lithium secondary battery can provide improved cycle characteristics and high-temperature storage characteristics.
摘要翻译：公开了一种包括阴极，阳极，电解质和隔膜的锂二次电池，其中阳极包括比表面积为3m 2 / g以下的负极活性物质，基于100重量份的电解质，电解质包含0.1〜6重量份的丙烷磺内酯类化合物。锂二次电池解决了在第一次充电循环时在阳极表面上使用增加量的形成SEI膜所需的丙烷磺内酯类化合物引起的性能下降的问题。此外，锂二次电池可以提供改进的循环特性和高温存储特性。

15. 发明申请

US20070048907A1 Methods of forming NMOS/PMOS transistors with source/drains including strained materials and devices so formed 有权
标题翻译：形成具有源极/漏极的NMOS / PMOS晶体管的方法，包括如此形成的应变材料和器件
公开(公告)号：US20070048907A1
公开(公告)日：2007-03-01
申请号：US11435968
申请日：2006-05-17
申请人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
发明人： Ho Lee , Tetsuji Ueno , Hwa-Sung Rhe
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02211 , H01L21/02293 , H01L21/3147 , H01L21/3148 , H01L21/3185 , H01L21/823814 , H01L29/045 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
摘要翻译：形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。

16. 发明申请

US20070015062A1 Additive for nonaqueous electrolyte and secondary battery using the same 有权
标题翻译：用于非水电解质和使用其的二次电池的添加剂
公开(公告)号：US20070015062A1
公开(公告)日：2007-01-18
申请号：US11479305
申请日：2006-06-30
申请人： Ho Lee , Tae Park , Yong Choi , Hong Park
发明人： Ho Lee , Tae Park , Yong Choi , Hong Park
IPC分类号： H01M10/40 , H01M2/16
CPC分类号： H01M10/0567 , H01M4/13 , H01M4/137 , H01M4/60 , H01M10/052 , H01M10/0568 , H01M10/0569 , H01M2004/027 , Y02T10/7011
摘要： Disclosed is an electrolyte for a battery, which comprises: (a) an electrolyte salt; (b) a solvent for electrolyte; and (c) a compound represented by the following formula 1: wherein R is a halogen atom, or a halogen-substituted or non-substituted C1˜C10 alkyl group or alkenyl group. An electrode comprising a passivation layer partially or totally formed on a surface thereof, wherein the passivation layer comprises a compound represented by the following Formula 1 or a chemical reaction product thereof, and a secondary battery using the electrolyte and/or the electrode are also disclosed. The compound can improve the initial charge/discharge efficiency and cycle life characteristics of a secondary battery, and can inhibit a battery from swelling under high-temperature storage conditions.
摘要翻译：公开了一种电池用电解质，其包括：（a）电解质盐; （b）电解质溶剂; 和（c）由下式1表示的化合物：其中R是卤素原子，或卤素取代或未取代的C1〜C10烷基或烯基。一种电极，包括部分或全部形成在其表面上的钝化层，其中钝化层包括由下式1表示的化合物或其化学反应产物，并且还公开了使用电解质和/或电极的二次电池。该化合物可以提高二次电池的初始充电/放电效率和循环寿命特性，并且可以抑制电池在高温储存条件下膨胀。

17. 发明申请

US20060221841A1 Method of monitoring link performance and diagnosing active link state in ethernet passive optical network 有权
标题翻译：监控链路性能和诊断以太网无源光网络中主动链路状态的方法
公开(公告)号：US20060221841A1
公开(公告)日：2006-10-05
申请号：US11286632
申请日：2005-11-22
申请人： Ho Lee , Jee Eun , Tae Whan Yoo , Bong Kim
发明人： Ho Lee , Jee Eun , Tae Whan Yoo , Bong Kim
IPC分类号： H04J3/14
CPC分类号： H04L43/0811 , H04L43/0847 , H04L43/16
摘要： Provided is a method of monitoring link performance and diagnosing an active link state without interrupting traffic in an Ethernet passive optical network (EPON) while the link is in the active state. The method of monitoring link performance and diagnosing an active link state without interrupting data flow to logic links which are in active states in the EPON, includes: a) allowing an operator of the EPON to select a link performance monitoring function or a link active state diagnosing function; b-1) if the link performance monitoring function is selected, setting a monitoring cycle timer and periodically transmitting a performance information request frame from a local node to a remote node; b-2) if the remote node receives the performance information request frame, collecting corresponding link performance information and transmitting a response frame from the remote node to the local node in a format which is predetermined in accordance with a corresponding frame format; b-3) if the local node receives the response frame from the remote node, analyzing the performance information of the response frame and determining whether the link performance has deteriorated or if a failure has occurred in the local node; b-4) if the deterioration of the link function or the degree of the failure reaches a predetermined threshold, reporting to an upper layer that a failure has occurred.
摘要翻译：提供了一种在链路处于活动状态时监视链路性能和诊断活动链路状态而不中断以太网无源光网络（EPON）中的业务的方法。监视链路性能和诊断活动链路状态而不中断到EPON中处于活动状态的逻辑链路的数据流的方法包括：a）允许EPON的运营商选择链路性能监视功能或链路活动状态诊断功能; b-1）如果选择了链路性能监视功能，则设置监视周期定时器并且周期地从本地节点向远程节点发送性能信息请求帧; b-2）如果所述远程节点接收到所述性能信息请求帧，则收集对应的链路性能信息，并以根据对应的帧格式预定的格式从所述远程节点向所述本地节点发送响应帧; b-3）如果本地节点从远程节点接收到响应帧，分析响应帧的性能信息，确定链路性能是否恶化，或者本地节点是否发生故障; b-4）如果链路功能的劣化或故障程度达到预定阈值，则向上层报告发生故障。

18. 发明申请

US20060131656A1 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US20060131656A1
公开(公告)日：2006-06-22
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

19. 发明申请

US20060088968A1 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US20060088968A1
公开(公告)日：2006-04-27
申请号：US11299447
申请日：2005-12-08
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

20. 发明申请

US20060038230A1 Transistor and method of manufacturing the same 有权
公开(公告)号：US20060038230A1
公开(公告)日：2006-02-23
申请号：US11207703
申请日：2005-08-19
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
IPC分类号： H01L27/12 , H01L29/06
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7834
摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

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