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11. 发明申请

US20150014745A1 Strained InGaAs Quantum Wells for Complementary Transistors 有权
标题翻译：应变InGaAs量子阱互补晶体管
公开(公告)号：US20150014745A1
公开(公告)日：2015-01-15
申请号：US14504559
申请日：2014-10-02
申请人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
发明人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
IPC分类号： H01L29/778 , H01L27/092
CPC分类号： H01L29/7783 , B82Y10/00 , H01L27/092 , H01L29/1079 , H01L29/151 , H01L29/20 , H01L29/365 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L31/035236
摘要： An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
摘要翻译：用于具有Sb基p沟道的互补晶体管的InGaAs n沟道量子阱异质结构。异质结构包括具有中间至n沟道材料和p沟道材料的晶格常数的缓冲层，并被构造成适应由n沟道和p沟道材料之间的晶格常数失配产生的应变。

12. 发明授权

US07558923B1 Prevention of live-lock in a multi-processor system 失效
标题翻译：防止多处理器系统中的实时锁定
公开(公告)号：US07558923B1
公开(公告)日：2009-07-07
申请号：US09470329
申请日：1999-12-22
申请人： Brian R. Bennett , Stephen S. Chang
发明人： Brian R. Bennett , Stephen S. Chang
IPC分类号： G06F12/08 , G06F13/18 , G06F5/00
CPC分类号： G06F12/0831 , G06F9/526
摘要： Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.
摘要翻译：本发明的一些实施例包括防止多处理器系统中的实时锁定的方法。该方法包括识别尝试修改资源的第一总线事务并且设置状态位以指示尝试修改共享资源的总线事务处于未决状态。该方法还包括重试针对共享资源的每个随后的非修改总线事务，直到状态位被清除。

13. 发明授权

US5694614A Minimum latency bus interface circuit with reduced I/O pin count through multi-mode operation 失效
标题翻译：最小延时总线接口电路通过多模式操作减少I / O引脚数
公开(公告)号：US5694614A
公开(公告)日：1997-12-02
申请号：US848985
申请日：1997-04-30
申请人： Brian R. Bennett
发明人： Brian R. Bennett
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： A method and apparatus for interfacing multiple integrated circuit chip devices to a system bus includes higher speed portions of a circuit within a primary IC chip and lower speed portions of a circuit within a secondary IC chip. The primary IC chip connects directly to the system bus while the secondary IC chip receives the same bus signals via the primary IC chip after a one clock cycle delay. Both the primary and secondary IC chips are capable of driving signals out onto the system bus when the primary and secondary ICs are part of a bus master circuit. When the primary and secondary ICs act as bus masters, signals are received by the secondary IC chip in the same clock cycle as the primary IC chip receives the signals. Thus, the secondary IC includes a state machine to indicate if the received signals are delayed by one clock cycle or not. In a preferred embodiment, the same pins are used by the primary IC to drive signals through to the secondary IC as to drive signals out onto the system bus.
摘要翻译：用于将多个集成电路芯片器件连接到系统总线的方法和装置包括初级IC芯片内的电路的较高速度部分和次级IC芯片内的电路的较低速度部分。主IC芯片直接连接到系统总线，而辅助IC芯片在一个时钟周期延迟后通过主IC芯片接收相同的总线信号。当主和次级IC都是总线主电路的一部分时，主IC芯片和辅助IC芯片能够将信号驱动到系统总线上。当主集成电路和次级IC作为总线主机时，辅助IC芯片在与主IC芯片接收信号相同的时钟周期中接收信号。因此，次级IC包括用于指示接收到的信号是否延迟一个时钟周期的状态机。在优选实施例中，主IC使用相同的引脚来驱动信号通过次级IC，以将信号驱动到系统总线上。

14. 发明授权

US09054169B2 Strained InGaAs quantum wells for complementary transistors 有权
标题翻译：用于互补晶体管的应变InGaAs量子阱
公开(公告)号：US09054169B2
公开(公告)日：2015-06-09
申请号：US14504559
申请日：2014-10-02
申请人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
发明人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
IPC分类号： H01L29/778 , H01L29/15 , H01L31/0352 , H01L29/36 , H01L29/66 , H01L29/10 , B82Y10/00 , H01L27/092 , H01L29/20
CPC分类号： H01L29/7783 , B82Y10/00 , H01L27/092 , H01L29/1079 , H01L29/151 , H01L29/20 , H01L29/365 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L31/035236
摘要： An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
摘要翻译：用于具有Sb基p沟道的互补晶体管的InGaAs n沟道量子阱异质结构。异质结构包括具有中间至n沟道材料和p沟道材料的晶格常数的缓冲层，并被构造成适应由n沟道和p沟道材料之间的晶格常数失配产生的应变。

15. 发明授权

US08884265B2 Strained InGaAs quantum wells for complementary transistors 有权
标题翻译：用于互补晶体管的应变InGaAs量子阱
公开(公告)号：US08884265B2
公开(公告)日：2014-11-11
申请号：US14156592
申请日：2014-01-16
申请人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
发明人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
IPC分类号： H01L21/24 , H01L29/15 , H01L29/778
CPC分类号： H01L29/7783 , B82Y10/00 , H01L27/092 , H01L29/1079 , H01L29/151 , H01L29/20 , H01L29/365 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L31/035236
摘要： An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
摘要翻译：用于具有Sb基p沟道的互补晶体管的InGaAs n沟道量子阱异质结构。异质结构包括具有中间至n沟道材料和p沟道材料的晶格常数的缓冲层，并被构造成适应由n沟道和p沟道材料之间的晶格常数失配产生的应变。

16. 发明申请

US20130149845A1 n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits 有权
标题翻译：具有单量子阱的n沟道场效应晶体管和p沟道场效应晶体管用于互补电路
公开(公告)号：US20130149845A1
公开(公告)日：2013-06-13
申请号：US13756566
申请日：2013-02-01
申请人： Brian R. Bennett , John Bradley Boos , Mario Ancona , James G. Champlain , Nicolas A. Papanicolaou
发明人： Brian R. Bennett , John Bradley Boos , Mario Ancona , James G. Champlain , Nicolas A. Papanicolaou
IPC分类号： H01L21/02
CPC分类号： H01L21/02398 , H01L21/02395 , H01L21/02466 , H01L21/02505 , H01L21/02549 , H01L27/0605
摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.
摘要翻译：在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。

17. 发明申请

US20110297916A1 N-and P-Channel Field-Effect Transistors with Single Quantum Well for Complementary Circuits 有权
标题翻译：具有单量子阱的N沟道场效应晶体管和P沟道场效应晶体管用于互补电路
公开(公告)号：US20110297916A1
公开(公告)日：2011-12-08
申请号：US13115453
申请日：2011-05-25
申请人： Brian R. Bennett , John Bradley Boos , Mario Ancona , James G. Champlain , Nicolas A. Papanicolaou
发明人： Brian R. Bennett , John Bradley Boos , Mario Ancona , James G. Champlain , Nicolas A. Papanicolaou
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/02398 , H01L21/02395 , H01L21/02466 , H01L21/02505 , H01L21/02549 , H01L27/0605
摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.
摘要翻译：在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。

18. 发明授权

US5590299A Multiprocessor system bus protocol for optimized accessing of interleaved storage modules 失效
标题翻译：多处理器系统总线协议，用于优化访问交错存储模块
公开(公告)号：US5590299A
公开(公告)日：1996-12-31
申请号：US331290
申请日：1994-10-28
申请人： Brian R. Bennett
发明人： Brian R. Bennett
IPC分类号： G06F12/02 , G06F12/06 , G06F13/18 , G06F12/00
CPC分类号： G06F13/18 , G06F12/0607 , G06F12/0215
摘要： A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.
摘要翻译：多处理器信息处理系统具有与多个CPU通信的交错存储器模块的系统总线。多处理器系统包括监视本地CPU请求的地址的子系统监视电路。如果本地CPU寻址与最后访问的存储器模块不同的存储器模块，则子系统监视电路启动一个请求以维持系统总线的控制。以这种方式，通常对交错的存储器模块进行顺序写入和读取操作，使得模块恢复时间的影响被最小化。子系统监视电路包括一个传输计数寄存器，指示在本地CPU必须放弃对系统总线的控制之前可以连续运行多少个数据传输周期。以这种方式，对于竞争控制系统总线的其他CPU，可以确保公平的仲裁。

19. 发明授权

US09006708B2 Low-resistivity p-type GaSb quantum wells 有权
标题翻译：低电阻率p型GaSb量子阱
公开(公告)号：US09006708B2
公开(公告)日：2015-04-14
申请号：US13895387
申请日：2013-05-16
申请人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
发明人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
IPC分类号： H01L29/12 , H01L29/205 , H01L29/778
CPC分类号： H01L29/122 , H01L29/201 , H01L29/205 , H01L29/7783 , H01L29/7784 , H01L29/7785
摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
摘要翻译：提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。异质结构包括InP衬底上的In0.52Al0.48As层，其中In0.52Al0.48As与InP晶格匹配，随后是In0.52Al0.48As层上的AlAsxSb1-x缓冲层，AlAsxSb1-x AlAsxSb1-x缓冲层上的间隔层，AlAsxSb1-x间隔层上的GaSb量子阱层，GaSb量子阱层上的AlAs x Sb 1-x势垒层，AlAs x Sb 1-x间隔层上的In 0.2 Al 0.8 Sb蚀刻停止层， x阻挡层和InAs帽。半导体器件适用于诸如场效应晶体管的低功率电子器件。

20. 发明申请

US20140217363A1 Low-Resistivity p-Type GaSb Quantum Wells 有权
标题翻译：低电阻率p型GaSb量子阱
公开(公告)号：US20140217363A1
公开(公告)日：2014-08-07
申请号：US13895387
申请日：2013-05-16
申请人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
发明人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
IPC分类号： H01L29/06
CPC分类号： H01L29/122 , H01L29/201 , H01L29/205 , H01L29/7783 , H01L29/7784 , H01L29/7785
摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
摘要翻译：提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。异质结构包括InP衬底上的In0.52Al0.48As层，其中In0.52Al0.48As与InP晶格匹配，随后是In0.52Al0.48As层上的AlAsxSb1-x缓冲层，AlAsxSb1-x AlAsxSb1-x缓冲层上的间隔层，AlAsxSb1-x间隔层上的GaSb量子阱层，GaSb量子阱层上的AlAs x Sb 1-x势垒层，AlAs x Sb 1-x间隔层上的In 0.2 Al 0.8 Sb蚀刻停止层， x阻挡层和InAs帽。半导体器件适用于诸如场效应晶体管的低功率电子器件。

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