专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20020177279A1 Method for making multiple threshold voltage fet using multiple work-function gate materials 有权
标题翻译：使用多个功能门材料制造多阈值电压的方法
公开(公告)号：US20020177279A1
公开(公告)日：2002-11-28
申请号：US10205143
申请日：2002-07-24
申请人： International Business Machines Corporation
发明人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L021/336
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

12. 发明申请

US20020132434A1 Stepped collector implant and method for fabrication 失效
标题翻译：步进式集电极植入物及其制造方法
公开(公告)号：US20020132434A1
公开(公告)日：2002-09-19
申请号：US09811859
申请日：2001-03-19
申请人： International Business Machines Corporation
发明人： Gregory G. Freeman , Basanth Jagannathan , Shwu-jen Jeng , Jeffrey B. Johnson
IPC分类号： H01L021/8222
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/36 , H01L29/66242
摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.
摘要翻译：本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。本发明的优选实施例通过阶梯式收集器掺杂物分布提供改进的高速性能，其通过寄生电容的最小增加来减少发射极 - 集电极传播时间和寄生电阻。优选的阶梯式收集器掺杂物分布包括浅植入物和更深的植入物。浅的注入降低了基极 - 集电极空间电荷区域宽度，降低电阻，并调整集电极 - 基极击穿特性。较深的植入物将埋藏的收集器连接到子集电极，并提供到子集电极的低电阻路径。阶梯式收集器掺杂物分布对器件本征区域外部的集电极 - 基极电容的影响最小，因为较高掺杂剂由本征区域之外的外部碱性掺杂剂补偿或埋入其中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式