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    • 11. 发明授权
    • Phase shifter, method of fabricating the same, and duplexer having the same
    • 移相器及其制造方法,以及具有该移相器的双工器
    • US07973618B2
    • 2011-07-05
    • US11644910
    • 2006-12-26
    • Kuang-woo NamIn-sang SongChul-soo KimYun-kwon Park
    • Kuang-woo NamIn-sang SongChul-soo KimYun-kwon Park
    • H03H7/46
    • H03H7/463H03H7/18
    • A phase shifter fabricated by a simple process and having a simple structure, a method of fabricating the same, and a duplexer having the same are disclosed. The duplexer includes a transmitting-end filter capable of passing only a signal in the range of a transmission frequency, a receiving-end filter capable of passing only a signal in the range of a reception frequency, and a phase shifter interposed between the transmitting-end filter and the receiving-end filter to isolate a transmitted signal of the transmitting-end filter and a received signal of the receiving-end filter from each other. The phase shifter includes a substrate provided with an input port and an output port, an inductor formed on the substrate and connected to the input and output ports, and a capacitor provided on the substrate, wherein the capacitor and inductor share a region of the substrate.
    • 公开了一种通过简单工艺制造并具有简单结构的移相器,其制造方法和具有该相移器的双工器。 双工器包括能够仅通过传输频率范围内的信号的发送端滤波器,仅能够接收接收频率范围内的信号的接收端滤波器和插入在发送频率范围之间的移相器, 端接滤波器和接收端滤波器,以将发送端滤波器的发送信号和接收端滤波器的接收信号彼此隔离。 移相器包括设置有输入端口和输出端口的基板,形成在基板上并连接到输入和输出端口的电感器和设置在基板上的电容器,其中电容器和电感器共享基板的区域 。
    • 14. 发明申请
    • Balun
    • 巴伦
    • US20070194860A1
    • 2007-08-23
    • US11638507
    • 2006-12-14
    • Chul-soo KimDal AhnKwi-soo KimIn-sang SongYun-kwon ParkSeok-chul YunKuang-woo Nam
    • Chul-soo KimDal AhnKwi-soo KimIn-sang SongYun-kwon ParkSeok-chul YunKuang-woo Nam
    • H03H5/00
    • H01P5/10
    • A balun capable of a reduced whole size. The balun includes an input line receiving an unbalanced signal, an output line receiving the unbalanced signal from the input line and outputting a balanced signal, and a ground part. The input and output lines are formed on a layer, and the ground part is formed on a different layer from the layer. The ground part includes an opening and is electrically connected to the input line, and a portion of the ground part is removed to form the opening so that a potential difference occurs between first and second output lines. Thus, although a length of the output line is less than ¼ of an input wavelength λ, a difference between phases of first and second output signals can be about 180°. As a result, the whole size of the balun can be reduced.
    • 平衡 - 不平衡转换器能够减小整体尺寸。 平衡 - 不平衡转换器包括接收不平衡信号的输入线,输入线接收来自输入线的不平衡信号并输出​​平衡信号的输出线和接地部分。 输入和输出线形成在层上,并且接地部分形成在与该层不同的层上。 接地部分包括开口并且电连接到输入线,并且去除接地部分的一部分以形成开口,使得在第一和第二输出线之间产生电位差。 因此,尽管输出线的长度小于输入波长λ的1/4,但是第一和第二输出信号的相位差可以是大约180°。 结果,平衡不平衡变换器的整体尺寸可以减小。
    • 16. 发明授权
    • Synchronous semiconductor memory device having multi-bank scheme
    • 具有多银行方案的同步半导体存储器件
    • US07203810B2
    • 2007-04-10
    • US10298553
    • 2002-11-19
    • Chul-soo Kim
    • Chul-soo Kim
    • G06F12/00
    • G11C7/1066G11C7/1042G11C7/1048G11C7/1072G11C11/4082G11C2207/2281G11C2207/229
    • A synchronous semiconductor memory device allows one memory bank to begin executing a data operation (e.g., reading data from a memory cell) while another memory bank is executing another data operation (e.g., writing data to a memory cell). The synchronous semiconductor memory device includes a write data path through which an input data signal is transmitted to the memory cell of a memory bank executing a write operation, and a read data path through which an output data signal is transmitted from the memory cell of a memory bank executing a read operation to an input/output pin. The read and write data paths are each connected to the memory banks via a common input/output line. The operation of the memory banks and the write and read data paths are synchronized, such that once a first memory bank begins executing either the write or read operation, a second memory bank may begin executing the other type of data operation after a predetermined time delay has elapsed, while the first memory bank is still executing its data operation.
    • 同步半导体存储器件允许一个存储器组开始执行数据操作(例如,从存储器单元读取数据),而另一个存储器组正在执行另一个数据操作(例如,将数据写入存储器单元)。 同步半导体存储器件包括写入数据路径,通过该写入数据路径将输入数据信号发送到执行写入操作的存储器组的存储单元,以及读取数据路径,通过该数据路径从a的存储器单元发送输出数据信号 存储器组对输入/输出引脚执行读操作。 读写数据路径通过公共输入/输出线连接到存储体。 存储体和写入和读取数据路径的操作被同步,使得一旦第一存储体开始执行写入或读取操作,则第二存储体可以在预定的时间延迟之后开始执行其他类型的数据操作 已经过去了,而第一个存储体仍在执行其数据操作。