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11. 发明申请

US20110228600A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

12. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

13. 发明授权

US08472224B2 Adjustable write bins for multi-level analog memories 失效
标题翻译：适用于多级模拟存储器的可调式写入箱
公开(公告)号：US08472224B2
公开(公告)日：2013-06-25
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译：通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。每个可能的仓包括一个或多个值。识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。从具有非重叠值的分组组中选择最大数量的分区。所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。

14. 发明申请

US20110069521A1 ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES 有权
标题翻译：用于多级模拟记忆体的可调写文字
公开(公告)号：US20110069521A1
公开(公告)日：2011-03-24
申请号：US12566430
申请日：2009-09-24
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00 , G11C11/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.
摘要翻译：具有可调节写入箱的模拟存储器，包括用于向存储器写入的系统。该系统包括解释一个或多个写入控制信号的写入装置，产生写入信号，以及在选择的存储器位置处施加写入信号以存储所需的内容。所选择的存储器位置受到数据相关噪声的影响，并且能够存储被分配到“n”个存储槽中的值的范围，其被配置为使得写入至少“n-1”个存储单元的平均成本在所选模拟存储器位置的目标成本。该系统还包括读取装置。该系统还包括写控制电路，其包括响应于期望内容选择一个或多个写入控制信号的写入信号选择器，所选择的存储器位置的当前内容以及与期望内容相关联的存储区。

15. 发明授权

US08495540B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 失效
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08495540B2
公开(公告)日：2013-07-23
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

16. 发明授权

US08407632B2 Detecting dose and focus variations during photolithography 失效
标题翻译：在光刻期间检测剂量和聚焦变化
公开(公告)号：US08407632B2
公开(公告)日：2013-03-26
申请号：US12881548
申请日：2010-09-14
申请人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
发明人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F7/70658
摘要： A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.
摘要翻译：在说明性实施例中提供了用于在光刻期间检测剂量和聚焦变化的方法，系统和计算机可用程序产品。在晶片上形成测试形状，该晶片用于制造集成电路，该测试形状使用为制造预定的剂量值和聚焦值形成。测量测试形状的电容。使用提取模型将电容解析为第二计量值和第二焦点值。计算给药值和第二给药值之间的差异。基于差异，建议制造中的剂量调整。

17. 发明授权

US08245169B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 有权
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08245169B2
公开(公告)日：2012-08-14
申请号：US12648456
申请日：2009-12-29
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

18. 发明申请

US20120165624A1 SIGNAL PROCESSING APPARATUS 失效
公开(公告)号：US20120165624A1
公开(公告)日：2012-06-28
申请号：US13397564
申请日：2012-02-15
申请人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
发明人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
IPC分类号： A61B5/0205 , A61B5/08 , A61B5/024 , A61B5/1455
CPC分类号： A61B5/0205 , A61B5/021 , A61B5/02154 , A61B5/024 , A61B5/029 , A61B5/0402 , A61B5/0476 , A61B5/0816 , A61B5/14532 , A61B5/14546 , A61B5/14551 , A61B5/14552 , A61B5/4821 , A61B5/7214 , A61B5/7246 , A61B5/7253 , A61B5/7257 , A61B5/726 , A61B6/00 , A61B8/00 , A61B8/5276 , G06K9/0051 , H04B1/123
摘要： The present invention involves a method and an apparatus for analyzing measured signals, including the determination of a measurement of oxygen saturation and respiration rate in the measured signals during a calculation of a physiological parameter of a monitored patient. Use of this invention is described in particular detail with respect to oximetry-based measurements but extends to other types of measurements.

19. 发明授权

US07921004B2 Methods and apparatus for analyzing transmission lines with decoupling of connectors and other circuit elements 有权
标题翻译：用于分析连接器和其他电路元件去耦的传输线的方法和装置
公开(公告)号：US07921004B2
公开(公告)日：2011-04-05
申请号：US12061269
申请日：2008-04-02
申请人： Ibrahim M. Elfadel , Hao Ming Huang , Albert E. Ruehli
发明人： Ibrahim M. Elfadel , Hao Ming Huang , Albert E. Ruehli
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and apparatus are provided for analyzing transmission lines with decoupling of connectors and other circuit elements. According to one aspect of the invention, circuits with one or more parasitic elements are analyzed by partitioning at least one of the parasitic elements in a transverse manner; identifying a plurality of subcircuits each comprised of partitioned circuit elements from the plurality of transmission lines and one or more parasitic elements in a given path; wherein each of the subcircuits is associated with a path in the circuit; performing a waveform relaxation analysis between each of the subcircuits; and repeating the step of performing the waveform relaxation analysis using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred. The circuit can optionally further comprise one or more transmission lines which would also be partitioned in a transverse manner.
摘要翻译：提供了用于分析连接器和其他电路元件去耦的传输线的方法和装置。根据本发明的一个方面，通过以横向方式分隔至少一个寄生元件来分析具有一个或多个寄生元件的电路; 识别多个子电路，每个子电路由来自所述多个传输线的分隔电路元件和给定路径中的一个或多个寄生元件组成; 其中每个子电路与电路中的路径相关联; 在每个子电路之间进行波形弛豫分析; 并且重复使用在前一次迭代中确定的波形执行波形弛豫分析的步骤，直到发生对所得波形的收敛。电路可以可选地进一步包括一个或多个也将以横向分隔的传输线。

20. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

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