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11. 发明授权

US09952986B2 Power delivery and data transmission using PCIe protocol via USB type-C port 有权
公开(公告)号：US09952986B2
公开(公告)日：2018-04-24
申请号：US14986268
申请日：2015-12-31
申请人： Intel Corporation
发明人： Akshay G. Pethe , David J. Harriman , Mahesh Wagh , Abdul Hawk Ismail
IPC分类号： G06F13/00 , G06F13/10 , G06F13/42 , G06F1/26 , G06F13/28 , G06F13/38 , G06F13/40 , G06F1/32
CPC分类号： G06F13/102 , G06F1/266 , G06F1/3203 , G06F13/287 , G06F13/387 , G06F13/4022 , G06F13/4221 , G06F13/4282
摘要： Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

12. 发明授权

US09921768B2 Low power entry in a shared memory link 有权
公开(公告)号：US09921768B2
公开(公告)日：2018-03-20
申请号：US14576125
申请日：2014-12-18
申请人： Intel Corporation
发明人： Michelle C. Jen , Debendra Das Sharma , Mahesh Wagh , Venkatraman Iyer
IPC分类号： G06F3/06 , G06F13/38 , G06F1/32
CPC分类号： G06F3/0625 , G06F1/3234 , G06F3/0659 , G06F3/0673 , G06F13/385
摘要： Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

13. 发明申请

US20170083475A1 MULTICHIP PACKAGE LINK 审中-公开
公开(公告)号：US20170083475A1
公开(公告)日：2017-03-23
申请号：US15039452
申请日：2013-12-26
申请人： Intel Corporation
发明人： Zuoguo J. Wu , Mahesh Wagh , Debendra Das Sharma , Gerald S. Pasdast , Ananthan Ayyasamy , Xiaobei Li , Robert G. Blankenship , Robert J. Safranek
IPC分类号： G06F13/42 , G06F15/173 , G06F13/12
CPC分类号： G06F13/4282 , G06F13/124 , G06F13/4273 , G06F15/173 , Y02D10/14 , Y02D10/151
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

14. 发明授权

US09547618B2 Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
标题翻译：为芯片上的系统（SoC）提供外围组件互连（PCI）兼容的事务级别协议，
公开(公告)号：US09547618B2
公开(公告)日：2017-01-17
申请号：US14262158
申请日：2014-04-25
申请人： INTEL CORPORATION
发明人： Ken Shoemaker , Mahesh Wagh , Woojong Han , Madhu Athreya , Arvind Mandhani , Shreekant S. Thakkar
IPC分类号： G06F13/20 , G06F13/42 , G06F13/36 , G06F13/40 , G06F13/38
CPC分类号： G06F13/404 , G06F13/385 , G06F13/4022 , G06F13/4027 , G06F13/4045
摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能无需修改即可并入设备。描述和要求保护其他实施例。

15. 发明授权

US09535838B2 Atomic operations in PCI express 有权
标题翻译： PCI Express中的原子操作
公开(公告)号：US09535838B2
公开(公告)日：2017-01-03
申请号：US13691106
申请日：2012-11-30
申请人： Intel Corporation
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F13/14 , G06F12/08 , G06F1/32 , H04L12/66 , G06F13/40 , G06F13/38 , G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

16. 发明授权

US09489322B2 Reducing latency of unified memory transactions 有权
标题翻译：减少统一内存事务的延迟
公开(公告)号：US09489322B2
公开(公告)日：2016-11-08
申请号：US14317308
申请日：2014-06-27
申请人： Intel Corporation
发明人： Mahesh Wagh , Prashanth Kalluraya
IPC分类号： H03M13/00 , G06F13/16 , G06F13/42 , H04L1/18
CPC分类号： G06F13/1631 , G06F13/4234 , H04L1/1867
摘要： In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，装置包括消耗逻辑，用于请求和处理包括关键数据部分和第二数据部分的数据，所述数据存储在耦合到插入在所述装置和所述存储器之间的处理器的存储器中。此外，该装置包括耦合到消费逻辑的协议栈逻辑，以经由处理器向存储器发出读请求，以响应于读请求来请求数据并接收多个完成。在一个实施例中，协议栈逻辑包括完成处理逻辑，用于在完成之后完成协议栈处理之前将第一个完成的数据发送到消费逻辑。描述和要求保护其他实施例。

17. 发明申请

US20160209911A1 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints 审中-公开
标题翻译：用于提高根端口和根端口集成端点恢复时间的方法，设备和系统
公开(公告)号：US20160209911A1
公开(公告)日：2016-07-21
申请号：US14998158
申请日：2015-12-24
申请人： Intel Corporation
发明人： Mahesh Wagh , Robert E. Gough
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/3246 , G06F1/325 , G06F9/4418 , G06F13/42 , H04L49/15 , Y02D10/151 , Y02D50/20
摘要： A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.
摘要翻译：芯片上的系统（SoC）具有多核处理器，二级（L2）高速缓存控制器，二级高速缓存，集成存储器控制器和串行点到点链路接口，以实现多核之间的通信处理器和设备。该接口实现协议栈，并且包括发送器，用于向设备发送串行数据，接收器反序列化输入串行流。协议栈支持多个功率管理状态，包括其中向设备提供电源电压的有效状态，第一关闭状态和不提供电源电压的第二关闭状态到设备。响应于设备准备进入活动状态的指示，协议栈提供在默认恢复时间到期之前访问设备以完成转换。

18. 发明申请

US20160179427A1 LOW POWER ENTRY IN A SHARED MEMORY LINK 有权
标题翻译：共享存储器链接中的低电源输入
公开(公告)号：US20160179427A1
公开(公告)日：2016-06-23
申请号：US14576125
申请日：2014-12-18
申请人： Intel Corporation
发明人： Michelle C. Jen , Debendra Das Sharma , Mahesh Wagh , Venkatraman Iyer
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F1/3234 , G06F3/0659 , G06F3/0673 , G06F13/385
摘要： Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.
摘要翻译：根据存储器访问链路协议，数据被发送以对应于通过链路与共享存储器相关联的加载/存储类型操作，并且存储器访问链路协议将被覆盖在另一不同的链路协议上。发送请求进入低功率状态，其中请求包括在令牌的字段中编码的数据值，令牌是指示分组数据的开始，并且进一步指示是否在后发送的后续数据令牌是根据其他链路协议和存储器访问链路协议之一来包括数据。

19. 发明申请

US20150161050A1 PCI EXPRESS PREFETCHING 有权
公开(公告)号：US20150161050A1
公开(公告)日：2015-06-11
申请号：US14583601
申请日：2014-12-27
申请人： Intel Corporation
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

20. 发明授权

US09032103B2 Transaction re-ordering 有权
标题翻译：交易重新订购
公开(公告)号：US09032103B2
公开(公告)日：2015-05-12
申请号：US13706575
申请日：2012-12-06
申请人： Intel Corporation
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F5/00 , G06F12/08 , G06F1/32 , H04L12/66 , G06F13/40 , G06F13/38 , G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

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