专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

AU8377098A Direct memory access (dma) transactions on a low pin count bus 未知
公开(公告)号：AU8377098A
公开(公告)日：1999-04-12
申请号：AU8377098
申请日：1998-06-26
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F13/28 , G06F3/00
摘要： A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

12. 发明专利

SG146429A1 TRUSTED INPUT FOR MOBILE PLATFORM TRANSACTIONS 未知
公开(公告)号：SG146429A1
公开(公告)日：2008-10-30
申请号：SG2004029500
申请日：2004-05-21
申请人： INTEL CORP
发明人： POISNER DAVID I
IPC分类号： G06F3/00 , G06F3/06 , G06F21/00 , G06F1/00 , G06F12/00
摘要： TRUSTED INPUT FOR MOBILE PLATFORM TRANSACTIONS According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), and a chipset coupled to the CPU including protected registers. The computer system also includes a micro-controller coupled to the chipset to perform scans to receive key-matrix data, wherein trusted software accesses the key-matrix data via the protected registers to ensure the authenticity of the data.

13. 发明专利

GB2345170B Memory transactions on a low pin count bus 未知
公开(公告)号：GB2345170B
公开(公告)日：2002-12-18
申请号：GB0007301
申请日：1998-07-07
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F12/00 , G06F13/16 , G06F13/10 , G06F13/42 , G06F9/445
摘要： A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

14. 发明专利

GB2345170A Memory transactions on a low pin count bus 未知
公开(公告)号：GB2345170A
公开(公告)日：2000-06-28
申请号：GB0007301
申请日：1998-07-07
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F12/00 , G06F13/16 , G06F13/10 , G06F13/42 , G06F9/445
摘要： A system having a bus (124) coupled to a host (102) and a memory device (108). The bus (124) may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device (108) may store system start-up information and communicate this information with the host (102) over the bus (124).

15. 发明公开

EP3049997A4 BIOMETRIC SENSORS FOR PERSONAL DEVICES 审中-公开
标题翻译： BIOMETRISCHE SENSORENFÜRPERSONALISIERTE VORRICHTUNGEN
公开(公告)号：EP3049997A4
公开(公告)日：2017-04-26
申请号：EP14868834
申请日：2014-09-26
申请人： INTEL CORP
发明人： PANT MONDIRA D , ABDELMONEUM MOHAMED A , KARNIK TANAY , PISENTI STEPHEN , POISNER DAVID I , MAHAMEED RASHED
IPC分类号： G06K9/00 , G01N29/265 , G06F21/32
CPC分类号： G01N29/265 , G01N2291/106 , G06F21/32 , G06F2221/2111 , G06K9/0002 , Y10T29/49005
摘要： Methods and systems may provide for a system having a flexible substrate, an ultrasonic transducer array coupled to the flexible substrate and a processor coupled to the ultrasonic transducer array. The processor may identify a fingerprint based on a signal from the ultrasonic transducer array. The system may also include an external component having a curved profile, wherein the ultrasonic transducer array is embedded in the external component and includes a read surface that conforms to the curved profile. In one example, the external component includes a button having a function that is separate from identification of the fingerprint.
摘要翻译：方法和系统可以提供具有柔性衬底，耦合到柔性衬底的超声换能器阵列和耦合到超声换能器阵列的处理器的系统。处理器可以基于来自超声换能器阵列的信号来识别指纹。该系统还可以包括具有弯曲轮廓的外部部件，其中超声波换能器阵列嵌入在外部部件中并且包括符合弯曲轮廓的读取表面。在一个示例中，外部组件包括具有与识别指纹分开的功能的按钮。

16. 发明公开

EP0979460A4 SYSTEM FOR CONTROLLING ACCESS TO A REGISTER MAPPED TO AN I/O ADDRESS SPACE OF A COMPUTER SYSTEM 失效
标题翻译： SYSTEM ZUR ZUGRIFFSKONTROLLE ZU EINEM寄存器AUFGENOMMEN IM ADDRESSENBEREICH EINES RECHNERSYSTEMS
公开(公告)号：EP0979460A4
公开(公告)日：2000-03-15
申请号：EP97929698
申请日：1997-05-22
申请人： INTEL CORP
发明人： POISNER DAVID I
IPC分类号： G06F13/10 , G06F9/38 , G06F15/00 , G06F12/14
CPC分类号： G06F9/3869
摘要： A method of providing access to an input/output (I/O) mapped register (60) of a computer system (18) is described. The computer system (18) includes a processor (20) operable in a system management mode (SMM), in which the processor (20) accesses a dedicated system management memory space, a real mode, a protected mode and a virtual 8086 mode. The method includes the steps of firstly receiving an access request at the I/O mapped register (60). Logic circuitry (64) associated with the I/O mapped register (60) then determines whether the processor (20) is operating in SMM by examining the status of a system management interrupt acknowledge (SMIACT#) output of the processor (20). If the logic circuitry (64) determines that the processor (20) is operating in SMM, a first, unrestricted type of access by the processor (20) to the I/O mapped register (60) is provided. Alternatively, if the logic circuitry (64) determines that the processor (20) is not operating in SMM, a second, restricted type of access by the processor (20) to the I/O mapped register (60) is provided. If the first, unrestricted type of access is provided to the processor (20), it performs an operation, under the direction of code stored in the dedicated system management memory address space, on the contents of the I/O mapped register (60).
摘要翻译：描述了提供对计算机系统（18）的输入/输出（I / O）映射寄存器（60）的访问的方法。计算机系统（18）包括可在系统管理模式（SMM）下操作的处理器（20），其中处理器（20）访问专用系统管理存储器空间，实模式，保护模式和虚拟8086模式。该方法包括首先在I / O映射寄存器（60）处接收访问请求的步骤。与I / O映射寄存器（60）相关联的逻辑电路（64）然后通过检查处理器（20）的系统管理中断确认（SMIACT＃）输出的状态来确定处理器（20）是否在SMM中操作。如果逻辑电路（64）确定处理器（20）以SMM操作，则提供处理器（20）对I / O映射寄存器（60）的第一无限制类型的访问。或者，如果逻辑电路（64）确定处理器（20）不在SMM中操作，则提供处理器（20）对I / O映射寄存器（60）的第二受限类型的访问。如果向处理器（20）提供第一种不受限制的访问类型，则它在存储在专用系统管理存储器地址空间中的代码的指导下在I / O映射寄存器（60）的内容上执行操作，。

17. 发明公开

EP2727331A4 ADAPTIVE TEXT FONT AND IMAGE ADJUSTMENTS IN SMART HANDHELD DEVICES FOR IMPROVED USABILITY 审中-公开
标题翻译：自适应TESTSCHRIFTART-和画质设定智能手持设备技术改进，采用
公开(公告)号：EP2727331A4
公开(公告)日：2015-06-17
申请号：EP12807708
申请日：2012-06-30
申请人： INTEL CORP
发明人： KRIMON YURI I , POISNER DAVID I
IPC分类号： H04N5/225 , G06F3/01 , G06F3/048 , G06F17/21 , G06K9/00 , G06K9/20 , G06K9/36 , G06T7/00 , G09G5/22 , G09G5/26 , H04N1/393
CPC分类号： G09G5/22 , G06F3/012 , G06F3/04847 , G06F17/214 , G06K9/00221 , G09G5/26 , G09G2320/08 , G09G2354/00

18. 发明公开

EP1021756A4 DIRECT MEMORY ACCESS (DMA) TRANSACTIONS ON A LOW PIN COUNT BUS 失效
标题翻译： DIREKT-SPEICHERZUGRIFF / TRANSAKTIONEN AUF EIN BUS MIT NIEDRIGER PINANZAHL
公开(公告)号：EP1021756A4
公开(公告)日：2000-12-20
申请号：EP98934188
申请日：1998-06-26
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： A system including a host (102) coupled to a memory device (108) and a peripheral controller device (120). The host (102) is coupled to the peripheral controller device (120) via bus (124) having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device (120) performs a direct memory access (DMA) transactions with the memory device (108) via the host (102) the bus (124).
摘要翻译：一种包括耦合到存储器设备（108）和外围控制器设备（120）的主机（102）的系统。主机（102）经由具有多个通用信号线的总线（124）耦合到外围控制器设备（120），以携带时分多路复用的地址，数据和控制信息。外围控制器设备（120）经由主机（102）与总线（124）执行与存储器设备（108）的直接存储器访问（DMA）事务。

19. 发明专利

MY146723A SYSTEM AND METHOD FOR PROTECTION AGAINST UNTRUSTED SYSTEM MANAGEMENT CODE BY REDIRECTING A SYSTEM MANAGEMENT INTERRUPT AND CREATING A VIRTUAL MACHINE CONTAINER 未知
公开(公告)号：MY146723A
公开(公告)日：2012-09-14
申请号：MYPI20032123
申请日：2003-06-06
申请人： INTEL CORP
发明人： SUTTON JAMES A II , GEORGE ROBERT T , BURGESS BRADLEY G , GRAWROCK DAVID W , UHLIG RICHARD A , POISNER DAVID I , GLEW ANDREW F , HALL CLIFFORD D , SMITH LAWRENCE O III , GILBERT NEIGER , KOZUCH MICHAEL A
IPC分类号： G06F9/46 , G06F1/00 , G06F12/14 , G06F9/48 , G06F21/00
摘要： A SYSTEM AND METHOD FOR PERMITTING THE EXECUTION OF SYSTEM MANAGEMENT MODE (SMM) CODE DURING SECURE OPERATIONS IN A MICROPROCESSOR SYSTEM IS DESCRIBED. IN ONE EMBODIMENT, THE SYSTEM MANAGEMENT INTERRUPT (SMI) MAY BE FIRST DIRECTED TO A HANDLER IN A SECURED VIRTUAL MACHINE MONITOR (SVMM). THE SMI MAY THEN BE REDIRECTED TO SMM CODE LOCATED IN A VIRTUAL MACHINE (VM) THAT IS UNDER THE SECURITY CONTROL OF THE SVMM. THIS REDIRECTION MAY BE ACCOMPLISHED BY ALLOWING THE SVMM TO READ AND WRITE THE SYSTEM MANAGEMENT (SM) BASE REGISTER IN THE PROCESSOR.

20. 发明专利

HK1028459A1 Direct memory access (dma) transactions on a low pin count bus. 未知
公开(公告)号：HK1028459A1
公开(公告)日：2001-02-16
申请号：HK00107601
申请日：2000-11-27
申请人： INTEL CORP
发明人： GAFKEN ANDREW H , BENNETT JOSEPH A , POISNER DAVID I
IPC分类号： G06F13/28 , G06F
摘要： A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式