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11. 发明申请

US20090097339A1 Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands 有权
标题翻译：具有内部命令生成器的集成电路存储器件，其中支持使用独立和相关命令的扩展命令集
公开(公告)号：US20090097339A1
公开(公告)日：2009-04-16
申请号：US12236978
申请日：2008-09-24
申请人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
发明人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.
摘要翻译：集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

12. 发明申请

US20100148819A1 Majority voter circuits and semiconductor device including the same 审中-公开
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US20100148819A1
公开(公告)日：2010-06-17
申请号：US12656590
申请日：2010-02-04
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-II Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-II Park
IPC分类号： H03K19/23 , H03K19/20
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

13. 发明申请

US20140019833A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20140019833A1
公开(公告)日：2014-01-16
申请号：US14031620
申请日：2013-09-19
申请人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

14. 发明授权

US08004328B2 AC-coupling phase interpolator and delay-locked loop using the same 失效
标题翻译：交流耦合相位内插器和使用其的延迟锁定环路
公开(公告)号：US08004328B2
公开(公告)日：2011-08-23
申请号：US12570186
申请日：2009-09-30
申请人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

15. 发明授权

US07843239B2 Dividing circuit and phase locked loop using the same 失效
标题翻译：分频电路和锁相环使用相同
公开(公告)号：US07843239B2
公开(公告)日：2010-11-30
申请号：US12318385
申请日：2008-12-29
申请人： Young-Soo Sohn , Kwang-II Park
发明人： Young-Soo Sohn , Kwang-II Park
IPC分类号： H03L7/06
CPC分类号： G06G7/16 , H03K21/023 , H03L7/0891 , H03L7/183
摘要： The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage.
摘要翻译： PLL包括选择信号发生器，其被配置为输出响应于第一时钟信号而变化的选择信号;以及第一分频电路，被配置为将外部输入的参考时钟信号除以除法比，并输出第一除法信号。第一分频电路响应于选择信号选择施加到第一分频信号的至少一个周期的参考时钟信号的多个边沿中的一个，并且基于所选择的边沿的同步并产生第一分频信号参考时钟信号。第二分频电路被配置为接收输出时钟信号，将输出时钟信号除以分频比，并输出第二除法信号。第二分频电路响应于选择信号选择施加到第二分频信号的至少一个周期的参考时钟信号的边沿中的一个，并且基于参考的所选择的边沿同步并产生第二除法信号时钟信号。同步信号输出部被配置为检测第一和第二除法信号之间的相位差，产生与相位差对应的控制电压，并输出具有与控制电压对应的频率的输出时钟信号。

16. 发明申请

US20100079180A1 AC-COUPLING PHASE INTERPOLATOR AND DELAY-LOCKED LOOP USING THE SAME 失效
标题翻译：交流耦合相位插补器和延迟锁定环使用相同
公开(公告)号：US20100079180A1
公开(公告)日：2010-04-01
申请号：US12570186
申请日：2009-09-30
申请人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/00 , H03H11/16
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

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