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11. 发明申请

US20050258858A1 Multichip package test 失效
公开(公告)号：US20050258858A1
公开(公告)日：2005-11-24
申请号：US11191494
申请日：2005-07-27
申请人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
发明人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3185
CPC分类号： G01R31/318505 , G01R31/318513
摘要： A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

12. 发明授权

US06841425B2 Wafer treatment method for protecting fuse box of semiconductor chip 失效
标题翻译：用于保护半导体芯片保险丝盒的晶片处理方法
公开(公告)号：US06841425B2
公开(公告)日：2005-01-11
申请号：US10282741
申请日：2002-10-28
申请人： Jae-Il Lee , Jeong-Ho Bang , Young-Moon Lee , Hyo-Geun Chae
发明人： Jae-Il Lee , Jeong-Ho Bang , Young-Moon Lee , Hyo-Geun Chae
IPC分类号： H01L21/82 , H01L23/31 , H01L23/525
CPC分类号： H01L23/3171 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Methods for treating a wafer to protect a fuse box of a semiconductor chip are provided. These methods include applying an insulating coating solution onto the surface of at least one of a plurality of fuse boxes in a semiconductor chip so as to prevent moisture or impurities from seeping into the fuse box. With these methods, the degradation of the semiconductor chip can be substantially reduced by protecting the fuse box from a high-temperature and very humid atmosphere, and impurities such as particles. Thus, characteristics and reliability of the semiconductor chip can be also improved.
摘要翻译：提供了用于处理晶片以保护半导体芯片的保险丝盒的方法。这些方法包括在半导体芯片中的多个保险丝盒中的至少一个的表面上施加绝缘涂层溶液，以防止水分或杂质渗入保险丝盒中。利用这些方法，通过保护熔丝盒免受高温和非常潮湿的气氛以及诸如颗粒的杂质，可以显着降低半导体芯片的劣化。因此，也可以提高半导体芯片的特性和可靠性。

13. 发明授权

US07602172B2 Test apparatus having multiple head boards at one handler and its test method 有权
标题翻译：在一个处理机上具有多个头板的测试装置及其测试方法
公开(公告)号：US07602172B2
公开(公告)日：2009-10-13
申请号：US12109299
申请日：2008-04-24
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

14. 发明授权

US07254757B2 Flash memory test system and method capable of test time reduction 失效
标题翻译：闪存测试系统和方法能够测试时间缩短
公开(公告)号：US07254757B2
公开(公告)日：2007-08-07
申请号：US10954834
申请日：2004-09-29
申请人： Dong-Kyoo Park , Jong-Kook Kim , Jeong-Ho Bang , Sang-Young Choi , Eun-Sik Kim
发明人： Dong-Kyoo Park , Jong-Kook Kim , Jeong-Ho Bang , Sang-Young Choi , Eun-Sik Kim
IPC分类号： G11C29/00 , G11C7/00 , G01R31/28
CPC分类号： G11C29/56004 , G11C29/56 , G11C2029/2602
摘要： A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.
摘要翻译：一种能够测试时间缩短的闪存测试系统和使用其的电测试方法。本发明提供一种包括第一存储器和第二存储器的并行测试器。第一和第二存储器用于将不同的数据提供给多个DUT中的相同地址，从而使得可以在并行测试中进行诸如修整测试，修复测试和无效块掩蔽测试。因此，进行并行测试来替代以前连续完成的测试。

15. 发明申请

US20050236688A1 Fuse regions of a semiconductor memory device and methods of fabricating the same 有权
标题翻译：半导体存储器件的保险丝区域及其制造方法
公开(公告)号：US20050236688A1
公开(公告)日：2005-10-27
申请号：US11108636
申请日：2005-04-19
申请人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
发明人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
IPC分类号： H01L21/82 , G11C17/16 , H01L21/4763 , H01L21/768 , H01L21/8246 , H01L23/525 , H01L27/112 , H01L29/40
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
摘要翻译：公开了一种制造熔丝区域的装置和方法。熔丝区域可以包括形成在衬底上的层间绝缘层，设置在层间绝缘层上的多个熔丝以及位于保险丝之间的熔断器隔离壁，其中每个保险丝隔离壁可以包括下部和上部熔丝隔离图案。

16. 发明授权

US07492032B2 Fuse regions of a semiconductor memory device and methods of fabricating the same 有权
标题翻译：半导体存储器件的保险丝区域及其制造方法
公开(公告)号：US07492032B2
公开(公告)日：2009-02-17
申请号：US11108636
申请日：2005-04-19
申请人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
发明人： Kwang-Kyu Bang , Kun-Gu Lee , Kyoung-Suk Lyu , Jeong-Ho Bang , Kyeong-Seon Shin , Ho-Jeong Choi , Seung-Gyoo Choi
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
摘要翻译：公开了一种制造熔丝区域的装置和方法。熔丝区域可以包括形成在衬底上的层间绝缘层，设置在层间绝缘层上的多个熔丝以及位于保险丝之间的熔断器隔离壁，其中每个保险丝隔离壁可以包括下部和上部熔丝隔离图案。

17. 发明申请

US20060158211A1 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US20060158211A1
公开(公告)日：2006-07-20
申请号：US11252448
申请日：2005-10-17
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/26
CPC分类号： G01R31/31926 , G01R31/31907
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

18. 发明申请

US20050102589A1 Flash memory test system and method capable of test time reduction 失效
标题翻译：闪存测试系统和方法能够测试时间缩短
公开(公告)号：US20050102589A1
公开(公告)日：2005-05-12
申请号：US10954834
申请日：2004-09-29
申请人： Dong-Kyoo Park , Jong-Kook Kim , Jeong-Ho Bang , Sang-Young Choi , Eun-Sik Kim
发明人： Dong-Kyoo Park , Jong-Kook Kim , Jeong-Ho Bang , Sang-Young Choi , Eun-Sik Kim
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00 , G11C29/56
CPC分类号： G11C29/56004 , G11C29/56 , G11C2029/2602
摘要： A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.
摘要翻译：一种能够测试时间缩短的闪存测试系统和使用其的电测试方法。本发明提供一种包括第一存储器和第二存储器的并行测试器。第一和第二存储器用于将不同的数据提供给多个DUT中的相同地址，从而使得可以在并行测试中进行诸如修整测试，修复测试和无效块掩蔽测试。因此，进行并行测试来替代以前连续完成的测试。

19. 发明授权

US5870086A Power saving display device and method for controlling power thereof 失效
标题翻译：省电显示装置及其功率控制方法
公开(公告)号：US5870086A
公开(公告)日：1999-02-09
申请号：US914028
申请日：1997-08-14
申请人： Jeong-Ho Bang
发明人： Jeong-Ho Bang
IPC分类号： G06F1/26 , G06F1/32 , G09G1/00 , G09G5/00 , H04N5/63
CPC分类号： G06F1/3218 , G09G1/005 , G09G2330/021
摘要： A power saving display device and a method for controlling power thereof. The power saving display device comprises a main power supply circuit for converting an output voltage from a power rectifier into desired voltages to be supplied to components in the display device, a synchronous signal discriminator for discriminating whether horizontal and vertical synchronous signals are inputted and generating first and second control signals for power management in accordance with the discriminated result, a main power interrupter for interrupting the operation of the main power supply circuit in response to the first control signal from the synchronous signal discriminator, an auxiliary power supply circuit being continuously operated in response to the output voltage from the power rectifier although the main power supply circuit is interrupted in operation, a heater power regulation circuit for varying a voltage being supplied to a heater of a cathode ray tube or maintaining it constantly in response to the second control signal from the synchronous signal discriminator, and a heater power connector for supplying an output voltage from the auxiliary power supply circuit to the heater power regulation circuit when the main power supply circuit is interrupted in operation.
摘要翻译：省电显示装置及其功率控制方法。省电显示装置包括用于将来自功率整流器的输出电压转换成要提供给显示装置中的部件的期望电压的主电源电路，用于鉴别是否输入水平和垂直同步信号的同步信号鉴别器，并且首先产生以及用于根据鉴别结果进行功率管理的第二控制信号，用于响应于来自同步信号鉴别器的第一控制信号中断主电源电路的操作的主电源中断器，辅助电源电路连续工作在响应于来自功率整流器的输出电压，尽管主电源电路在操作中被中断，加热器功率调节电路用于改变被提供给阴极射线管的加热器的电压或者响应于第二控制信号而不断地保持来自同步信号卷边器和加热器电源连接器，用于当主电源电路在操作中断时，将辅助电源电路的输出电压提供给加热器功率调节电路。

20. 发明授权

US06813195B2 Pipe latch circuit for outputting data with high speed 有权
标题翻译：用于高速输出数据的管锁电路
公开(公告)号：US06813195B2
公开(公告)日：2004-11-02
申请号：US10620901
申请日：2003-07-16
申请人： Jeong-Ho Bang , Ki-Jun Nam
发明人： Jeong-Ho Bang , Ki-Jun Nam
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/103 , G11C7/1051
摘要： It is an objective of the present invention to provide a pipe latch circuit with simpler control, smaller footprint, and higher speed operation. For this purpose, the present invention provides a pipe latch circuit for storing a sequentially received plurality of first data and second data and outputting them as rising edge output data or falling edge output data.
摘要翻译：本发明的目的是提供一种具有更简单控制，更小占地面积和更高速度操作的管锁电路。为此，本发明提供一种用于存储顺序接收的多个第一数据和第二数据并作为上升沿输出数据或下降沿输出数据输出的管锁存电路。

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