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11. 发明授权

US08420492B2 MOS transistor and method for forming the same 有权
标题翻译： MOS晶体管及其形成方法
公开(公告)号：US08420492B2
公开(公告)日：2013-04-16
申请号：US13143591
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Da Yang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Da Yang , Chao Zhao
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78 , H01L29/7845
摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.
摘要翻译：本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

12. 发明授权

US09425288B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09425288B2
公开(公告)日：2016-08-23
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源/漏区接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

13. 发明申请

US20150311319A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150311319A1
公开(公告)日：2015-10-29
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

14. 发明授权

US08642433B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08642433B2
公开(公告)日：2014-02-04
申请号：US13509551
申请日：2011-12-05
申请人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/336 , H01L21/477
CPC分类号： H01L29/6653 , H01L29/78
摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.
摘要翻译：公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

15. 发明申请

US20130045588A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130045588A1
公开(公告)日：2013-02-21
申请号：US13509551
申请日：2011-12-05
申请人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Jun Luo , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/20
CPC分类号： H01L29/6653 , H01L29/78
摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.
摘要翻译：公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

16. 发明授权

US08686534B2 Trench isolation structure and method for forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US08686534B2
公开(公告)日：2014-04-01
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底中并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

17. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

18. 发明授权

US08455323B2 Method for manufacturing semiconductor wafer 有权
标题翻译：制造半导体晶片的方法
公开(公告)号：US08455323B2
公开(公告)日：2013-06-04
申请号：US13201125
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L21/336
CPC分类号： H01L21/3221
摘要： There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
摘要翻译：提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

19. 发明申请

US20130062708A1 SEMICONDUCTOR DEVICE STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING FIN 有权
标题翻译：半导体器件结构，其制造方法和制造FIN的方法
公开(公告)号：US20130062708A1
公开(公告)日：2013-03-14
申请号：US13577942
申请日：2011-11-18
申请人： Huicai Zhong , Qingqing Liang , Jun Luo , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Jun Luo , Chao Zhao
IPC分类号： H01L21/762 , H01L27/088
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.
摘要翻译：公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

20. 发明申请

US20120168829A1 MOS TRANSISTOR AND METHOD FOR FORMING THE SAME 有权
标题翻译： MOS晶体管及其形成方法
公开(公告)号：US20120168829A1
公开(公告)日：2012-07-05
申请号：US13143591
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Da Yang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Da Yang , Chao Zhao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78 , H01L29/7845
摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.
摘要翻译：本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

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