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11. 发明授权

US07986211B2 Inductor 有权
标题翻译：电感器
公开(公告)号：US07986211B2
公开(公告)日：2011-07-26
申请号：US12968022
申请日：2010-12-14
申请人： Seong-il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Seong-il Kim , Jongmin Lee , Byoung-Gue Min , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F2017/0086 , H01L28/10
摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.
摘要翻译：提供一种电感器。电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线连接到第一至第四导电端子中的第一和第三导电端子。

12. 发明申请

US20120098099A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120098099A1
公开(公告)日：2012-04-26
申请号：US13193670
申请日：2011-07-29
申请人： Jongmin LEE , Byoung-Gue Min , Seong-il Kim , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
发明人： Jongmin LEE , Byoung-Gue Min , Seong-il Kim , Hyung Sup Yoon , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01L27/06 , H01L21/8222
CPC分类号： H01L27/0605 , H01L21/8252 , H01L29/732 , H01L29/93 , H03C1/36
摘要： Provided are a compound semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate including a first region and a second region; a transistor including first to third conductive impurity layers stacked on the substrate of the first region; and a variable capacitance diode spaced apart from the transistor of the first region and including the first and second conductive impurity layers stacked on the substrate of the second region.
摘要翻译：提供一种化合物半导体器件及其制造方法。半导体器件包括：衬底，其包括第一区域和第二区域; 晶体管，包括堆叠在所述第一区域的所述衬底上的第一至第三导电杂质层; 以及与第一区域的晶体管间隔开并且包括堆叠在第二区域的衬底上的第一和第二导电杂质层的可变电容二极管。

13. 发明授权

US08722474B2 Semiconductor device including stepped gate electrode and fabrication method thereof 有权
标题翻译：包括阶梯式栅电极的半导体器件及其制造方法
公开(公告)号：US08722474B2
公开(公告)日：2014-05-13
申请号：US13592589
申请日：2012-08-23
申请人： Hyung Sup Yoon , Byoung-Gue Min , Jong Min Lee , Seong-Il Kim , Dong Min Kang , Ho Kyun Ahn , Jong-Won Lim , Jae Kyoung Mun , Eun Soo Nam
发明人： Hyung Sup Yoon , Byoung-Gue Min , Jong Min Lee , Seong-Il Kim , Dong Min Kang , Ho Kyun Ahn , Jong-Won Lim , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L21/338
CPC分类号： H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.
摘要翻译：本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

14. 发明授权

US08853821B2 Vertical capacitors and methods of forming the same 有权
标题翻译：垂直电容器及其形成方法
公开(公告)号：US08853821B2
公开(公告)日：2014-10-07
申请号：US13618873
申请日：2012-09-14
申请人： Seong-il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jongmin Lee , Byoung-Gue Min , Jae Kyoung Mun , Eun Soo Nam
发明人： Seong-il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jongmin Lee , Byoung-Gue Min , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.
摘要翻译：提供垂直电容器及其形成方法。垂直电容器的形成可以包括在衬底的顶表面上形成输入和输出电极，蚀刻衬底的底表面以形成通孔电极，然后在通孔电极之间形成电介质层。结果，可以在基板的小区域中提供具有高电容的垂直电容器。

15. 发明申请

US20110140175A1 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME 失效
标题翻译：单片微波集成电路装置及其形成方法
公开(公告)号：US20110140175A1
公开(公告)日：2011-06-16
申请号：US12832432
申请日：2010-07-08
申请人： Byoung-Gue MIN , Jongmin Lee , Seong-ll Kim , Hyung Sup Yoon
发明人： Byoung-Gue MIN , Jongmin Lee , Seong-ll Kim , Hyung Sup Yoon
IPC分类号： H01L27/06 , H01L21/8222
CPC分类号： H01L29/66318 , H01L21/8252 , H01L27/0605 , H01L29/66204 , H01L29/7371 , H01L29/868
摘要： Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.
摘要翻译：提供了一种单片微波集成电路器件及其形成方法。该方法包括：在基底的异质结双极晶体管（HBT）区域和PIN二极管区域上形成子集电极层，集电极层，基极层，发射极层和发射极盖层; 在HBT区域中形成发射极图案和发射极盖图案，并通过图案化发射极层和发射极盖层而使基底层曝光; 并且通过用第一类型杂质掺杂PIN二极管区域的集电极层的一部分来形成本征区域，PIN二极管区域与HBT区域间隔开。

16. 发明申请

US20070128752A1 Method of fabricating T-gate 有权
标题翻译：制造T型门的方法
公开(公告)号：US20070128752A1
公开(公告)日：2007-06-07
申请号：US11607417
申请日：2006-12-01
申请人： Jae Yoeb Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
发明人： Jae Yoeb Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/0331 , H01L21/28587
摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.
摘要翻译：提供一种制造T型栅极的方法。该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

17. 发明授权

US06204102B1 Method of fabricating compound semiconductor devices using lift-off of insulating film 有权
标题翻译：使用绝缘膜剥离制造复合半导体器件的方法
公开(公告)号：US06204102B1
公开(公告)日：2001-03-20
申请号：US09207512
申请日：1998-12-09
申请人： Hyung Sup Yoon , Jin Hee Lee , Byung Sun Park , Chul Soon Park , Kwang Eui Pyun
发明人： Hyung Sup Yoon , Jin Hee Lee , Byung Sun Park , Chul Soon Park , Kwang Eui Pyun
IPC分类号： H01L21338
CPC分类号： B82Y10/00 , H01L21/28587 , H01L29/66469 , H01L29/66878
摘要： A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.
摘要翻译：一种形成化合物半导体器件的栅电极的方法包括：形成具有第一孔的第一绝缘膜图案，在第一绝缘膜图案上形成具有由反V型构成的第二孔的第二绝缘膜图案，形成T 通过在整个结构上沉积导电膜，去除第二绝缘膜图案，通过蚀刻第一绝缘膜图案在极侧壁上形成绝缘隔离物，并通过自发形成源极和漏极的欧姆电极，使用T型栅电极作为掩模的对准方法。因此，通过使用绝缘膜，可以防止诸如难熔金属的材料的T型栅极电极由于高退火而被稳定地形成。通过自对准方法形成的欧姆金属和栅电极可以通过在这些电极之间形成绝缘膜间隔来防止互连。

18. 发明授权

US07468295B2 Method of fabricating T-gate 有权
标题翻译：制造T型门的方法
公开(公告)号：US07468295B2
公开(公告)日：2008-12-23
申请号：US11607417
申请日：2006-12-01
申请人： Jae Yoeb Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
发明人： Jae Yoeb Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
IPC分类号： H01L21/338
CPC分类号： H01L21/0331 , H01L21/28587
摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.
摘要翻译：提供一种制造T型栅极的方法。该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

19. 发明授权

US08124489B2 Monolithic microwave integrated circuit device and method of forming the same 失效
标题翻译：单片微波集成电路器件及其形成方法
公开(公告)号：US08124489B2
公开(公告)日：2012-02-28
申请号：US12832432
申请日：2010-07-08
申请人： Byoung-Gue Min , Jongmin Lee , Seong-Il Kim , Hyung Sup Yoon
发明人： Byoung-Gue Min , Jongmin Lee , Seong-Il Kim , Hyung Sup Yoon
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L21/8252 , H01L27/0605 , H01L29/66204 , H01L29/7371 , H01L29/868
摘要： Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.
摘要翻译：提供了一种单片微波集成电路器件及其形成方法。该方法包括：在基底的异质结双极晶体管（HBT）区域和PIN二极管区域上形成子集电极层，集电极层，基极层，发射极层和发射极盖层; 在HBT区域中形成发射极图案和发射极盖图案，并通过图案化发射极层和发射极盖层而使基底层曝光; 并且通过用第一类型杂质掺杂PIN二极管区域的集电极层的一部分来形成本征区域，PIN二极管区域与HBT区域间隔开。

20. 发明授权

US07915106B2 Method of fabricating T-gate 失效
标题翻译：制造T型门的方法
公开(公告)号：US07915106B2
公开(公告)日：2011-03-29
申请号：US12270016
申请日：2008-11-13
申请人： Jae Yeob Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
发明人： Jae Yeob Shim , Hyung Sup Yoon , Dong Min Kang , Ju Yeon Hong , Kyung Ho Lee
IPC分类号： H01L21/338 , H01L21/44 , H01L21/28
CPC分类号： H01L21/0331 , H01L21/28587
摘要： A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.
摘要翻译：提供一种制造T型栅极的方法。该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

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