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11. 发明申请

US20110292742A1 Stacked Semiconductor Memory Device, Memory System Including The Same, And Method Of Repairing Defects Of Through Silicon Vias 有权
标题翻译：堆叠的半导体存储器件，包括其的存储器系统以及修复通孔硅缺陷的方法
公开(公告)号：US20110292742A1
公开(公告)日：2011-12-01
申请号：US13085776
申请日：2011-04-13
申请人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
发明人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
IPC分类号： G11C7/10 , H01L23/48
CPC分类号： G11C29/702 , G11C7/10 , H01L22/22 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06541
摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.
摘要翻译：根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

12. 发明授权

US08254184B2 Semiconductor memory device having a latency controller 有权
标题翻译：具有等待时间控制器的半导体存储器件
公开(公告)号：US08254184B2
公开(公告)日：2012-08-28
申请号：US12820364
申请日：2010-06-22
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/109 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
摘要翻译：半导体存储器件包括提供省电效果的等待时间控制器。等待时间控制器包括先进先出（FIFO）寄存器。在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

13. 发明授权

US08189403B2 High speed linear differential amplifier 有权
标题翻译：高速线性差分放大器
公开(公告)号：US08189403B2
公开(公告)日：2012-05-29
申请号：US12817760
申请日：2010-06-17
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： G11C7/00 , H03L7/00
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/78 , H03F2203/45382 , H03F2203/45384 , H03F2203/45454 , H03F2203/45466 , H03F2203/45702
摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
摘要翻译：具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

14. 发明申请

US20110001562A1 HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER 有权
标题翻译：高速线性差分放大器
公开(公告)号：US20110001562A1
公开(公告)日：2011-01-06
申请号：US12817760
申请日：2010-06-17
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/78 , H03F2203/45382 , H03F2203/45384 , H03F2203/45454 , H03F2203/45466 , H03F2203/45702
摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
摘要翻译：具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

15. 发明申请

US20060176988A1 Receiving apparatus and method thereof 有权
标题翻译：接收装置及其方法
公开(公告)号：US20060176988A1
公开(公告)日：2006-08-10
申请号：US11345451
申请日：2006-02-02
申请人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
发明人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
IPC分类号： H04B1/10
CPC分类号： H04L25/03038 , H04L7/0058
摘要： A receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient based on the plurality of internal clock signals and the input signal. The equalization receiving unit may adjust a received data signal based on the determined offset value and equalization coefficient.
摘要翻译：一种接收装置及其方法。在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。均衡接收单元可以基于多个内部时钟信号和输入信号确定偏移值和均衡系数。均衡接收单元可以基于确定的偏移值和均衡系数来调整接收的数据信号。

16. 发明授权

US07822111B2 Receiving apparatus and method thereof 有权
标题翻译：接收装置及其方法
公开(公告)号：US07822111B2
公开(公告)日：2010-10-26
申请号：US11345451
申请日：2006-02-02
申请人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
发明人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03038 , H04L7/0058
摘要： Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.
摘要翻译：示例性实施例涉及一种接收设备及其方法。在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。均衡接收单元可以在初始设置模式中确定偏移值和均衡系数，并且可以基于所确定的偏移值和均衡系数来调整接收的数据信号。

17. 发明申请

US20140019833A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20140019833A1
公开(公告)日：2014-01-16
申请号：US14031620
申请日：2013-09-19
申请人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

18. 发明授权

US07368949B2 Output driver and output driving method for enhancing initial output data using timing 有权
标题翻译：输出驱动器和输出驱动方法，用于使用定时来增强初始输出数据
公开(公告)号：US07368949B2
公开(公告)日：2008-05-06
申请号：US11561765
申请日：2006-11-20
申请人： Young-Soo Sohn , Jung-Hwan Choi
发明人： Young-Soo Sohn , Jung-Hwan Choi
IPC分类号： H03K19/094 , H03D1/06
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1069
摘要： An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.
摘要翻译：用于使用定时增强初始输出数据的输出驱动器包括用于产生选择信号的选择信号生成单元，用于产生参考数据的参考数据生成单元和选择单元。选择信号在输入数据的转变点处被激活，在等于或大于预定持续时间数的位数周期中，在保持相同的逻辑状态之后产生。参考数据从输入数据延迟一个比一个位周期短的延迟时间。驱动选择单元，以响应于选择信号，根据输入数据和参考数据中的任何一个的逻辑状态的转变来转换输出数据的逻辑状态。

19. 发明申请

US20050265440A1 Decision feedback equalization input buffer 有权
标题翻译：决策反馈均衡输入缓冲区
公开(公告)号：US20050265440A1
公开(公告)日：2005-12-01
申请号：US11040808
申请日：2005-01-21
申请人： Young-Soo Sohn
发明人： Young-Soo Sohn
IPC分类号： H03L7/00 , H03K5/159 , H03L7/081
CPC分类号： H03L7/0814 , H04L7/0087 , H04L7/0331 , H04L25/03057
摘要： In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.
摘要翻译：在判决反馈均衡（DFE）输入缓冲器中，诸如由符号间干扰（ISI）引起的定时和电压误差被完全补偿。施加可变均衡系数，其适应并补偿可能在一定范围的操作条件下产生的定时误差TE或电压误差VE的范围。以这种方式，实现了精确的补偿，允许更大的信号可靠性和更高的电路间传输速率。判决反馈均衡（DFE）输入缓冲器包括均衡器，该均衡器响应于可变均衡控制信号放大输入信号和过采样信号之间的电压电平差，均衡器产生放大的输出信号。采样单元响应于采样时钟信号对放大的输出信号进行采样以产生过采样信号。相位检测器响应于过采样信号的相位产生用于控制采样时钟信号的激活定时的定时控制信号。均衡控制器响应于定时控制信号修改可变均衡控制信号。

20. 发明授权

US07542507B2 Decision feedback equalization input buffer 有权
标题翻译：决策反馈均衡输入缓冲区
公开(公告)号：US07542507B2
公开(公告)日：2009-06-02
申请号：US11040808
申请日：2005-01-21
申请人： Young-Soo Sohn
发明人： Young-Soo Sohn
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20 , H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H03L7/0814 , H04L7/0087 , H04L7/0331 , H04L25/03057
摘要： In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.
摘要翻译：在判决反馈均衡（DFE）输入缓冲器中，诸如由符号间干扰（ISI）引起的定时和电压误差被完全补偿。施加可变均衡系数，其适应并补偿可能在一定范围的操作条件下产生的定时误差TE或电压误差VE的范围。以这种方式，实现了精确的补偿，允许更大的信号可靠性和更高的电路间传输速率。判决反馈均衡（DFE）输入缓冲器包括均衡器，该均衡器响应于可变均衡控制信号放大输入信号和过采样信号之间的电压电平差，均衡器产生放大的输出信号。采样单元响应于采样时钟信号对放大的输出信号进行采样以产生过采样信号。相位检测器响应于过采样信号的相位产生用于控制采样时钟信号的激活定时的定时控制信号。均衡控制器响应于定时控制信号修改可变均衡控制信号。

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