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11. 发明申请

US20100226165A1 RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF 有权
标题翻译：具有堆叠结构的电阻式存储器件及其操作方法
公开(公告)号：US20100226165A1
公开(公告)日：2010-09-09
申请号：US12714950
申请日：2010-03-01
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C7/1045 , G11C5/02 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2211/5641 , G11C2213/71 , G11C2213/72 , G11C2213/79
摘要： A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.
摘要翻译：存储器件包括堆叠在半导体衬底上的多个电阻存储器单元层的堆叠电阻性存储单元阵列，其中相应的存储单元层被配置为根据包括每个单元的位数的各自的程序模式来存储数据。该存储装置还包括控制电路，该控制电路被配置为响应于地址信号来识别所选择的存储器单元层的编程模式，并且根据所识别的程序模式响应于地址信号访问所选择的存储单元层。程序模式可以包括单级单元模式和至少一个多级单元模式。

12. 发明授权

US08589767B2 Systems, devices and methods using redundant error correction code bit storage 有权
标题翻译：使用冗余纠错码位存储的系统，设备和方法
公开(公告)号：US08589767B2
公开(公告)日：2013-11-19
申请号：US12713853
申请日：2010-02-26
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.
摘要翻译：诸如半导体存储器件的器件包括多个存储器单元，每个存储单元被配置为存储至少一个数据位和多个纠错码（ECC）单元，配置为冗余地存储用于存储器单元的ECC位。根据一些实施例，多个ECC单元包括配置成存储ECC位及其补码的多对ECC单元。根据另外的实施例，多个ECC小区包括被配置为存储ECC比特的相同副本的至少三个ECC小区的多个组。

13. 发明授权

US08422328B2 Semiconductor device, semiconductor system including the same, and voltage supply method of semiconductor device 有权
标题翻译：半导体器件，包括其的半导体系统以及半导体器件的电压供给方法
公开(公告)号：US08422328B2
公开(公告)日：2013-04-16
申请号：US12652209
申请日：2010-01-05
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C8/14
摘要： A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory devices.
摘要翻译：提供半导体器件，包括该半导体器件的半导体系统和半导体器件的电压供给方法。半导体器件包括至少两个半导体存储器件和被配置为选择性地向至少两个半导体存储器件中的每一个提供电压的电压供给控制器。

14. 发明授权

US08374052B2 Information storage devices using magnetic domain wall movement and methods of operating the same 有权
标题翻译：信息存储设备采用磁畴壁运动和操作方式相同
公开(公告)号：US08374052B2
公开(公告)日：2013-02-12
申请号：US12775160
申请日：2010-05-06
申请人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
发明人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
IPC分类号： G11C8/00 , G11C11/14
CPC分类号： G11C11/1653 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data.
摘要翻译：信息存储装置包括第一部分，其首先包括至少一个磁道，第一部分中的至少一个磁道中的每一个包括第一多个磁畴，并且被配置为在其中存储第一类型的数据，部分包括第二至少一个磁道，第二部分中的至少一个磁道中的每一个包括第二多个磁畴，并且被配置为在其中存储第二类型的数据，第二类型的数据与第一类数据。

15. 发明授权

US08345464B2 Resistive memory devices having a stacked structure and methods of operation thereof 有权
标题翻译：具有堆叠结构的电阻式存储器件及其操作方法
公开(公告)号：US08345464B2
公开(公告)日：2013-01-01
申请号：US12714950
申请日：2010-03-01
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/1045 , G11C5/02 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2211/5641 , G11C2213/71 , G11C2213/72 , G11C2213/79
摘要： A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.
摘要翻译：存储器件包括堆叠在半导体衬底上的多个电阻存储器单元层的堆叠电阻性存储单元阵列，其中相应的存储单元层被配置为根据包括每个单元的位数的各自的程序模式来存储数据。该存储装置还包括控制电路，该控制电路被配置为响应于地址信号来识别所选择的存储器单元层的编程模式，并且根据所识别的程序模式响应于地址信号访问所选择的存储单元层。程序模式可以包括单级单元模式和至少一个多级单元模式。

16. 发明申请

US20100223532A1 SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE 有权
标题翻译：使用冗余错误修正代码位存储的系统，设备和方法
公开(公告)号：US20100223532A1
公开(公告)日：2010-09-02
申请号：US12713853
申请日：2010-02-26
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.
摘要翻译：诸如半导体存储器件的器件包括多个存储器单元，每个存储单元被配置为存储至少一个数据位和多个纠错码（ECC）单元，配置为冗余地存储用于存储器单元的ECC位。根据一些实施例，多个ECC单元包括配置成存储ECC位及其补码的多对ECC单元。根据另外的实施例，多个ECC小区包括被配置为存储ECC比特的相同副本的至少三个ECC小区的多个组。

17. 发明申请

US20100214862A1 Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same 有权
标题翻译：用于改变工作特性的半导体器件和方法及包括其的半导体系统
公开(公告)号：US20100214862A1
公开(公告)日：2010-08-26
申请号：US12706756
申请日：2010-02-17
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Jung Min Lee , Seung Eon Ahn
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Hyun Ho Choi , Jung Min Lee , Seung Eon Ahn
IPC分类号： G11C5/14 , G11C8/08
CPC分类号： G11C5/14 , G11C5/147 , G11C7/22 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402 , G11C2207/2254
摘要： A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage.
摘要翻译：提供了一种改变半导体器件中的参数的方法。该方法包括在存储区域中接收和存储数据; 以及根据存储在存储器中的数据，在用于访问包括在半导体器件的存储器核心中的非易失性存储单元的参数的DC特性和AC定时特性之间改变至少一个。

18. 发明申请

US20100085826A1 Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same 有权
标题翻译：用于测量存储单元和包括其的半导体系统的电阻分布的测试电路
公开(公告)号：US20100085826A1
公开(公告)日：2010-04-08
申请号：US12588192
申请日：2009-10-07
申请人： Sang Beom Kang , Ho Jung Kim
发明人： Sang Beom Kang , Ho Jung Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/16 , G11C29/50008
摘要： The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
摘要翻译：用于测量存储单元的电阻分布的测试电路包括感测电路和数字值产生电路。感测电路将参考电压与接收与电阻元件连接的位线的电压的感测节点的电压进行比较，并产生感测信号。响应于来自感测电路的感测信号，数字值产生电路产生对应于位线的电阻 - 电容（RC）延迟的数字值。

19. 发明授权

US08144535B2 Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same 有权
标题翻译：用于测量存储器单元和包括其的半导体系统的电阻分布的测试电路
公开(公告)号：US08144535B2
公开(公告)日：2012-03-27
申请号：US12588192
申请日：2009-10-07
申请人： Sang Beom Kang , Ho Jung Kim
发明人： Sang Beom Kang , Ho Jung Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/16 , G11C29/50008
摘要： The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
摘要翻译：用于测量存储单元的电阻分布的测试电路包括感测电路和数字值产生电路。感测电路将参考电压与接收与电阻元件连接的位线的电压的感测节点的电压进行比较，并产生感测信号。响应于来自感测电路的感测信号，数字值产生电路产生对应于位线的电阻 - 电容（RC）延迟的数字值。

20. 发明授权

US08301835B2 Apparatuses and methods providing redundant array of independent disks access to non-volatile memory chips 有权
标题翻译：提供独立磁盘的冗余阵列访问非易失性存储器芯片的装置和方法
公开(公告)号：US08301835B2
公开(公告)日：2012-10-30
申请号：US12713559
申请日：2010-02-26
申请人： Ho Jung Kim
发明人： Ho Jung Kim
IPC分类号： G06F12/00
CPC分类号： G06F3/0658 , G06F3/0619 , G06F3/0688 , G06F11/108
摘要： A controller may include a RAID controller and an access controller. The RAID controller exchanges data with a host and select ones of a plurality of RAID levels responsive to RAID level information. The access controller is connected to the RAID controller and to a plurality of channels that are each connected to a plurality of non-volatile memory chips. The access controller accesses data in at least one of the non-volatile memory chips connected to each of the channels according to the selected RAID level. The controller may alternatively or additionally include a storage device and a main processor. The main processor is configured to logically partition a plurality of non-volatile memory chips that are connected to each of a plurality of channels into a normal partition region and a RAID level partition region, where data access is performed according to a selected RAID level, in response partition information that is stored in the storage device.
摘要翻译：控制器可以包括RAID控制器和访问控制器。 RAID控制器与主机交换数据，并根据RAID级别信息选择多个RAID级别中的一个。访问控制器连接到RAID控制器和连接到多个非易失性存储器芯片的多个通道。访问控制器根据所选择的RAID级别访问连接到每个信道的至少一个非易失性存储器芯片中的数据。控制器可以可选地或另外包括存储设备和主处理器。主处理器被配置为将连接到多个通道中的每一个的多个非易失性存储器芯片逻辑地分割成正常分区区域和RAID级别分区区域，其中根据所选择的RAID级别执行数据访问，在存储在存储设备中的响应分区信息中。

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