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11. 发明专利

JPH11353233A DATA CACHING METHOD FOR TRANSFER MEMORY AND BUS CONVERTING DEVICE 失效
公开(公告)号：JPH11353233A
公开(公告)日：1999-12-24
申请号：JP16018398
申请日：1998-06-09
申请人： HITACHI LTD
发明人： YONEDA KENICHI , TOMIZAWA HIROSHI , INADA SHUNJI , WATANABE SHIZUYA
IPC分类号： G06F12/08 , G06F13/36
摘要： PROBLEM TO BE SOLVED: To obtain a high hit rate even when data in a different transfer cycle are stored in a cache memory by determining the time up to the invalidation of data stored in the cache memory according to transfer cycles of data in a transfer memory stored in the cache memory. SOLUTION: A caching sequencer 19 which receives a cache-OFF signal stops outputting an enable signal to a comparator 23. Consequently, the caching of a block No.3 is turned off. The caching is turned off in a transfer cycle T1 as the time when the data of the transfer memory are updated and the data stored in the cache memory 17 can also be made effectively for the time as long as intervals of data update of the transfer memory. Consequently, the data of the transfer memory stored in the cache memory 17 are effective up to the time when the data of the transfer memory are updated, so the highest hit rate of the cache memory 17 can be obtained.

12. 发明专利

JPH09149073A DATA COMMUNICATION METHOD AND DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPH09149073A
公开(公告)日：1997-06-06
申请号：JP30159795
申请日：1995-11-20
申请人： HITACHI LTD
发明人： WATANABE SHIZUYA , TOMIZAWA HIROSHI
IPC分类号： G06F13/00 , H04L12/28 , H04L12/46
摘要： PROBLEM TO BE SOLVED: To set an IP(interface protocol) address easily and quickly from a specific data communication equipment to each of IP address setting requirement data communication equipments (including after exchange). SOLUTION: When an IP address request frame with a station number allocated to an IP address unsetting data communication equipment 3-1 is received by a specific data communication equipment 6-1 from the electrode 3-1 including a data communication equipment after exchange, the equipment 6-1 sends the IP address retrieved from a station IP table with the station number to the equipment 3-1 as an IP address setting frame. Then they are set to an IP address storage medium 8 quickly.

13. 发明专利

JPH0926943A DATA COMMUNICATION METHOD AND EQUIPMENT THEREFOR 失效
公开(公告)号：JPH0926943A
公开(公告)日：1997-01-28
申请号：JP17639495
申请日：1995-07-12
申请人： HITACHI LTD
发明人： WATANABE SHIZUYA , TOMIZAWA HIROSHI , OGAWA HISAO , INADA SHUNJI , ANPO OSAMU
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To transmit the large volume of data in a system for transmitting only cyclic data with a change and to hold the reliability of the data even when reception omission or the like is generated. SOLUTION: When respective plural stations 15 connected to a transmission line 8 transmit and receive the cyclic data and the respective stations 15 hold the cyclic data of the present station and the cyclic data of the other stations in a cyclic memory 2, the respective stations 15 detect only the data with the change among the cyclic data, transfer the data from the cyclic memory 2 to a memory 6 for transmission and transmit the stored data of the memory 6 for transmission to the other stations. Since the cyclic memory 2 is not accessed at the time of the transmission, access is not competed with another CPU or the like and the large volume of the data can be transmitted. Also, since all the cyclic data of the present station are cyclically transmitted to the other stations in a cycle longer than the cycle of transmitting only the data with the change, the reliability of the data is improved.

14. 发明专利

JPH06274463A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPH06274463A
公开(公告)日：1994-09-30
申请号：JP6041493
申请日：1993-03-19
申请人： HITACHI LTD
发明人： OOKURA TAKANORI , HAMADA TAKUSHI , INADA SHUNJI , YAMAGUCHI SHINICHIRO , TOMIZAWA HIROSHI
IPC分类号： G06F15/16 , G06F13/36 , G06F15/173 , G06F15/177 , H04L12/40
摘要： PURPOSE:To provide a data communication system in which the load of a system bus at the time of periodic data transmission can be reduced, and the occupancy rate of a data transmission line at the time of periodic data transmission and reception can be reduced. CONSTITUTION:Plural control computers are connected with a data transmission line 5, and each control computer is connected between a CPU (1-1-1-2), main memory 2, and system bus 4, and the data transmission line 5. Each control computer is equipped with a communication controller 3 incorporating a control part 6 and a periodic data memory 7. The periodically obtained cyclic data are transmitted and received through the data transmission line 5, and a required data processing is operated by the CPU 1 by using the storage periodic data in the main memory 2. The communication controller 3 receives the cyclic data necessary at least for its own control computer. The received periodic data are stored in the main memory 2, and only the updated periodic data are read from among the periodic data to be transmitted stored in the main memory 2 are read, and transmitted to the data transmission line 5.

15. 发明专利

JPH06103098A INFORMATION PROCESSOR 失效
公开(公告)号：JPH06103098A
公开(公告)日：1994-04-15
申请号：JP24949892
申请日：1992-09-18
申请人： HITACHI LTD
发明人： KUMAKURA KIKUYA , OKADA MASAKAZU , TOMIZAWA HIROSHI , SATAKE MASAHITO
IPC分类号： G06F11/00 , G06F11/34 , G06F13/00
摘要： PURPOSE:To prevent a fault of one function module from affecting other function modules by stopping the function of the function module after saving fault information in a nonvolatile storage circuit with the output of a serious fault detecting circuit. CONSTITUTION:If serious faults occurs to respective function modules, the serious fault detecting circuit 103 detects the serious faults first. Then a means 105 which stops the function after saving the fault information saves the fault information generated in the function module in the nonvolatile storage circuit 106. A display means 108 indicates that the fault information is saved in the nonvolatile storage circuit 106 and the means 105 which stops the function after saving the fault information stops the function of the function module. Therefore, even if the serious fault detecting circuit 103 gets out of order, the function module can be stopped after the fault information is stored in the nonvolatile storage circuit 106 since a forcible storage indicating circuit 104 is provided.

16. 发明专利

JPH0547012B2 失效
公开(公告)号：JPH0547012B2
公开(公告)日：1993-07-15
申请号：JP7668785
申请日：1985-04-12
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , YASUMOTO SEIICHI , OKADA MASAKAZU , TAKAHASHI MASAHIRO , HAMADA TAKUSHI
IPC分类号： H04L12/40

17. 发明专利

JPH0447827A ABNORMAL DATA COMMUNICATING PREVENTING SYSTEM FOR LOOP NETWORK 失效
公开(公告)号：JPH0447827A
公开(公告)日：1992-02-18
申请号：JP15671690
申请日：1990-06-15
申请人： HITACHI CABLE , HITACHI LTD
发明人： KURIYAMA MASARU , HAYAMA HIROYUKI , TOMIZAWA HIROSHI
IPC分类号： H04L12/42
摘要： PURPOSE:To prevent an abnormal data from flowing to a terminal by stopping transmitting a data received from a channel to the terminal by each node executing fully duplex communication in the case of generating abnormality in the node connected to the terminal as a communicating party. CONSTITUTION:Assuming that a node 1d on a terminal A side breaks down, a monitoring cycle is not t1 for a bit monitoring part 65 for monitoring a node 1b on a terminal B side. Assuming that the bit monitoring part 65 for monitor turns the output to '1'. Consequently, the output to the terminal B at a reception part 64 of the node 1b is turned to a Mark state ('1' at all times), and the transmission of the data received from the channel to the terminal B is stopped. Thus, at the terminal B, the data transmitted by the terminal itself is not returned as it is. Similarly, even when the abnormality is generated at the node 1b, the output is turned to '1' and the output to the terminal A is turned to the Mark state. Therefore, for the terminal A, the data transmitted by the terminal itself is not returned as it is.

18. 发明专利

JPH0368236A SYSTEM FOR PREVENTING ABNORMAL DATA COMMUNICATION IN LOOP NETWORK 失效
公开(公告)号：JPH0368236A
公开(公告)日：1991-03-25
申请号：JP20286389
申请日：1989-08-07
申请人： HITACHI CABLE , HITACHI LTD
发明人： HAYAMA HIROYUKI , TOMIZAWA HIROSHI
IPC分类号： H04L12/42
摘要： PURPOSE:To prevent abnormal data communication to a receiving terminal by providing a one-bit area for monitor in a channel and quickly detecting abnormality in a node at the receiving terminal side in case of the occurrence of the abnormality in a node on the transmitting terminal side. CONSTITUTION:At the time of sending data from a terminal A to a terminal B, a bit transmitting part 52 for monitor transmits a signal, which is repeatedly turned on and off at intervals of a certain time, to a bit 23 for monitor in the channel during data transmission. A bit non-change detecting part 55 for monitor in a receiving part 54 monitors contents of the received bit 23 and sets the detected output to '0' during the change of turning-on/off, and the detected output is set to '1' when the change of turning-on/off is not detected for a certain time or longer. That is, the output of the detecting part 55 is set to '1' and the output to the terminal B is set to the mark state when the bit 23 is not turned on/off because of the occurrence of abnormality in the node. Thus, abnormal data in the channel is prevented from flowing to the terminal B to improve the reliability of a system.

19. 发明专利

JPH0319742B2 失效
公开(公告)号：JPH0319742B2
公开(公告)日：1991-03-15
申请号：JP20147884
申请日：1984-09-28
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , IDE TOSHUKI , YASUMOTO SEIICHI , OKADA MASAKAZU , MIZOKAWA SADAO , OONUKI TAKESHI , SATAKE MASAHITO

20. 发明专利

JPH0116065B2 失效
公开(公告)号：JPH0116065B2
公开(公告)日：1989-03-22
申请号：JP19332582
申请日：1982-11-05
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , MIZOKAWA SADAO , HAMADA TAKUSHI , OKADA MASAKAZU , OONUKI TAKESHI
IPC分类号： H04L12/437

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