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11. 发明专利

JPH02356A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02356A
公开(公告)日：1990-01-05
申请号：JP12170688
申请日：1988-05-20
申请人： HITACHI LTD
发明人： TANIDA YUJI , HAGIWARA TAKAAKI , KONDO RYUJI , MINAMI SHINICHI , ITO YOKICHI
IPC分类号： H01L21/8247 , H01L21/822 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To minimize the size while improving the operating speed of a storage circuit device in which semiconductor non-volatile storing elements are used, by forming and extending zigzag a reference potential line and a digit line of memory cells and connecting them to the regions of the memory cells. CONSTITUTION:A plurality of element forming regions CH1, CH2 are arranged linearly on a semiconductor substrate and these element forming regions are halved alternately, so that source regions 94a-94d and drain regions 92a-92d of memory cells are formed. An interconnecting layer ED1 for providing a reference potential line is formed on the source regions 94a-94d and it is connected with the source regions through contact holes CNT1, CNT3, CNT5. An interconnection layer D1 for providing a digit line is formed on the drain regions 92a-92d and it is connected with the drain regions through contact holes CNT2, CNT4. These interconnecting layers ED1 and D1 are formed zigzag so as to decrease the area occupied by the interconnection layers.

12. 发明专利

JPS6477160A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6477160A
公开(公告)日：1989-03-23
申请号：JP23418787
申请日：1987-09-18
申请人： HITACHI LTD
发明人： KOMORI KAZUHIRO , HAGIWARA TAKAAKI , MEGURO SATOSHI , NISHIMOTO TOSHIAKI , WADA TAKESHI , UCHIBORI KIYOBUMI , MUTO TADASHI
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To improve the read-out of data in speed and the write of data in property by a method wherein the write of data is executed in such a manner that a second semiconductor region connected with a ground wire, a first semiconductor region connected with a data wire, and a control gate electrode are supplied with a high, a low, and a high potential respectively, and the read-out of data is performed in such a manner as a control gate electrode is supplied with a required potential as the first and the second semiconductor region are made to serve as a source and a drain respectively. CONSTITUTION:The write of data is executed by applying a high potential to a second semiconductor region (n layers 9, 10) connected with a ground wire SL and a control gate 7, and a low potential to a first semiconductor region (n layer 12) connected with a data line DL. The read-out of data is performed in such a manner that a control gate 7 is supplied with 5V, for example, as the first semiconductor region (n layer 12) and the second semiconductor region (n layers 9, 10) connected with the ground wire SL are made to serve as a source and a drain respectively. By these processes, the electric field is made to be intensified at the end of the ground line on the channel side during the write of data, so that a write property can be improved. And, a junction capacitance between an n-type semiconductor region 12 and a substrate 1 is made to decrease during the read-out of data is performed, consequently the read-out can be improved in speed.

13. 发明专利

JPS6476769A HIGH POWER SEMICONDUCTOR DEVICE WITH NONVOLATILE MEMORY 失效
公开(公告)号：JPS6476769A
公开(公告)日：1989-03-22
申请号：JP23211587
申请日：1987-09-18
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , OKABE TAKEAKI , NAGATA MINORU , OTAKA SHIGEO , HAGIWARA TAKAAKI
IPC分类号： H01L29/78 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To unnecessitate a gate bias circuit even in the ON state, and realize the saving of power and the preventing of an accident of service interruption, by using a device having a nonvolatile memory function, in the main body of a power MOSFET or its bias circuit. CONSTITUTION:When the source 3 of a high power MOSFET Q1 acting as a main switch is grounded, a drain 4 is connected to a load terminal, and a gate 5 is connected to the floating gate terminal 6 of a MOSFET Q2 having function of electrically rewritable nonvolatile memory. A second gate terminal 8 of Q2 is grounded, a drain terminal 7 is connected to a bias circuit. By electric charge stored in the floating gate terminal 6 of Q2, the gate terminal 5 of Q1 is biased, and Q1 turns ON. Once Q1 turns ON, the ON state of Q1 is maintained, even if the bias circuit connected to the terminal 7 of Q2 is eliminated, if only charge stored in the terminal 6 is kept. On the contrary, in the case of making Q1 turn ON, the terminal 7 is reverse-biased.

14. 发明专利

JPS63146434A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63146434A
公开(公告)日：1988-06-18
申请号：JP29230586
申请日：1986-12-10
申请人： HITACHI LTD
发明人： HAGIWARA TAKAAKI , IZAWA RYUICHI , MINAMI SHINICHI
IPC分类号： H01L21/8247 , G11C11/401 , G11C17/00 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/10 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To easily use information by providing a chip including a cell for storing chip-handling information and also providing a circuit for externally outputting the information directly or through a predetermined process. CONSTITUTION:A memory cell area 3 for storing information regarding a handling explanation and a circuit 4 for processing the information are provided in a chip 1 in addition to a section 2 for originally processing. The section 2 may be any of a microcomputer, a memory and an analog circuit. The capacity of the cell 3 for storing the information depends upon the section 2. For example, when the section 2 is of a memory, a catalog for explaining the handling is normally composed of approx. 10000 characters.

15. 发明专利

JPS62276878A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62276878A
公开(公告)日：1987-12-01
申请号：JP11921586
申请日：1986-05-26
申请人： HITACHI LTD
发明人： KOMORI KAZUHIRO , MEGURO SATOSHI , HAGIWARA TAKAAKI , KUME HITOSHI , TSUKADA TOSHIHISA , YAMAMOTO HIDEAKI
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/8247 , H01L27/06 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To decrease a write voltage and improve elimination efficiency by providing a drain region consisting of high density layers as well as a source region having a lower density than that of the drain region at least at end portions of channel region side. CONSTITUTION:A drain region of memory cell Qm comprising floating gate electrodes 5 and MISFET having control gate electrodes 7 is composed of high density layers and makes density of end portions of channel region side in a source region lower. While, the drain region consists of n -type semiconductor region 9 and n -type semiconductor region 10 and the source region consists of n -type semiconductor region 9, n -type semiconductor 10 as well as n -type semiconductor 11. These situations allow an electric field to be intensified at the end portions of drain region to increase the development of hot-electrons, resulting in decrease of write-voltage. Furthermore, an avalanche breakdown voltage between the source region and semiconductor substrate 1 is so raised that elimination efficiency becomes higher.

16. 发明专利

JPS62274773A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62274773A
公开(公告)日：1987-11-28
申请号：JP11733786
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUME HITOSHI , OKURA OSAMU , HAGIWARA TAKAAKI , SHIMIZU AKIHIRO , OOKI NAGATOSHI
IPC分类号： G11C11/402 , G11C11/405 , H01L21/8234 , H01L21/8242 , H01L27/00 , H01L27/088 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize a dynamic random access memory cell, small in cell area and excellent in memory-holding capability and long-term reliability, by a method wherein a WRITE transistor of a three-dimensional laminated structure is equipped with a type of conductivity different from that of two lower-layer transistors. CONSTITUTION:In a cell of this design, the type of conductivity of a WRITE- dedicated transistor T2 of a three-dimensional laminated structure is different from that of two lower-layer transistors T1 and T3. At the same time, in this way, a laminated CMOS may be built to constitute a peripheral circuit, which eliminates need for any masking process to create difference between an N- channel element and p-channel element. When, specifically, the transistor T2 is of the P-channel type and Tl and T3 of the M-channel type, the lower-layer transistor T1 and T3 will be further microstructuralized, and the WRITE- dedicated transistor T2 will be improved in lts leak or breakdown strength against kink phenomena.

17. 发明专利

JPS62229978A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62229978A
公开(公告)日：1987-10-08
申请号：JP7124486
申请日：1986-03-31
申请人： HITACHI LTD
发明人： YADORI SHOJI , WADA YASUO , HAGIWARA TAKAAKI , TAMURA MASAO
IPC分类号： H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/78
摘要： PURPOSE:To relax the field strength in the direction parallel to a channel at the end part of a high-impurity concentration drain region and to make larger the drain withstand voltage by a method wherein the high-impurity concentration drain region is formed in the semiconductor layer provided on the upper part of the low-impurty concentration drain region provided in a semiconductor substrate. CONSTITUTION:Low-impurity concentration source and drain regions 7 and 8 are formed in an Si substrate 1 and afterward, a B ion beam is implanted through a poly Si film 20 and a gate oxide film 4, which are formed on those regions, and a high-impurity concentration channel layer 14 is formed by performing a thermal annealing. Then, the two-layer film of the poly Si film and the oxide film is processed by a photo etching method and a gate electrode 15 and a gate protection insulating film 6 are formed. After that, an oxide film formed by a CVD method is etched and gate sidewall insulating films 9 are formed. Then, the poly Si film is grown by a CVD method and after a high-concentration As ion implantation and a high- temperature and short-time annealing are performed, the poly Si film is processed by a photo etching method and a source Si electrode 15 and a drain Si electrode 16 are formed. Lastly, an interlayer insulating film 12 is formed, a contact hole opening is performed and by forming Al electrodes 13, an MOSFET is completed.

18. 发明专利

JPS6271268A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6271268A
公开(公告)日：1987-04-01
申请号：JP11725286
申请日：1986-05-23
申请人： HITACHI LTD
发明人： TANIDA YUJI , HAGIWARA TAKAAKI , KONDO RYUJI , MINAMI SHINICHI , ITO YOKICHI
IPC分类号： G11C17/00 , G11C16/06 , H01L21/8234 , H01L21/8246 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a semiconductor memory circuit device having fast operating speed by using as a semiconductor nonvolatile memory cell an insulated gate field effect transistor having a gate insulated film of 2-layer structure. CONSTITUTION:An N-type single crystal Si wafer 1 is thermally oxidized to form an SiO2 film 2, and an Si3N4 film 3 is further formed. Then, the film 2 is exposed by a photoetching method, with a resist film 4 as a mask B ions are implanted to form P-type semiconductor regions 5, 6, the film 4 is removed, a well is diffused. Then, the film 3 is removed, the SiO2 film is exposed, phosphorus ions are implanted to the entire surface to form N-type semiconductor regions 20-22. Then, after the all SiO2 film on the Si surface is removed, an SiO2 film 24 is formed on the overall surface, and an Si3N4 film is further formed. Then, the exposed Si3N4 film is removed by a photoetching method except the photoresist film on the prescribed region, the film 24 is exposed, B ions are implanted to form P-type semiconductor layers 41-46, the resist film is removed, and field-oxidized.

19. 发明专利

JPS6223156A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6223156A
公开(公告)日：1987-01-31
申请号：JP16183585
申请日：1985-07-24
申请人： HITACHI LTD
发明人： NAKAI MASAAKI , WADA YASUO , HAGIWARA TAKAAKI , NAKAMURA TORU , KUME HITOSHI
IPC分类号： H01L21/761 , H01L21/76 , H01L27/14 , H01L27/146 , H04N5/335 , H04N5/359 , H04N5/369 , H04N5/372 , H04N5/374
摘要： PURPOSE:To shield a predetermined region, and to prevent the deterioration in performance such as the increase in parasitic capacitance by selectively forming a high concentration layer only around a drain. CONSTITUTION:A thick oxide film 130 shaped onto a P-type Si substrate 9 is removed selectively, and a thin oxide film 131 is formed through re-oxidation. Boron ions accelerated at high voltage are focussed in approximately 1mum through a focussed ion-beam technique, and scanned 132, and boron ions 133 are driven onto the substrate, thus shaping a high concentration layer 134. The periphery 135 of a driving section in the oxide film 130 is inclined, thus shaping the peripheral section 135 of the high concentration layer 134 in a self-alignment manner. The oxide film is removed selectively, a gate oxide film 136 is formed through re-oxidation, polycrystalline Si 138 as a gate electrode is shaped selectively, and N layers 137 as a source and a drain are formed through the implantation of As ions in the self-alignment manner.

20. 发明专利

JPS61267358A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61267358A
公开(公告)日：1986-11-26
申请号：JP10811885
申请日：1985-05-22
申请人： HITACHI LTD
发明人： KAGA TORU , HAGIWARA TAKAAKI , HORIUCHI KATSUTADA , KUME HITOSHI , IGURA YASUO , HAMADA AKIYOSHI
IPC分类号： H01L27/095 , H01L21/337 , H01L21/8232 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/80 , H01L29/808
摘要： PURPOSE:To obtain an ultrafine and highly reliable complementary semiconductor device by introducing a junction type field effect element into a complementary semiconductor device. CONSTITUTION:A P-type well 22 is provided on an N-type Si substrate 21, whose well includes therein a junction type field effect transistor (JFET) comprising an N-type channel region 23, a source-drain high-density N-type impurity region 24, and a gate 25 formed of a P-type impurity. The other surface portion of the N-type Si substrate includes a JFET comprising a P-type channel region 26, a source-drain high-density N-type impurity region 27, and a gate 28 formed of an N-type impurity. Since no thin gate oxide film is used, the device is enabled to be made ultrafine without considering reduction of the life of the gate oxide film, thereby accomplishing low-power consumption and high-speed circuit operation.

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