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    • 11. 发明授权
    • Diode having low forward voltage drop
    • 二极管具有低正向压降
    • US07491982B2
    • 2009-02-17
    • US11320641
    • 2005-12-30
    • Hideki Takahashi
    • Hideki Takahashi
    • H01L29/74
    • H01L29/404H01L29/0619H01L29/8611
    • A semiconductor device, including: a semiconductor substrate of the first conductivity type having a first surface and a second surface; a base region of the second conductivity type formed on the first surface of the semiconductor substrate; a guard ring region of the second conductivity type formed around the base region, and having the second type impurity of which concentration is lower than that of the base region; a first electrode formed on the base region; and a second electrode formed on the second surface of the semiconductor substrate, further including a base peripheral region formed around the base region and being connected to the base region, wherein the base peripheral region is deeper than the base region and has the substantially constant depth, and the concentration of the second conductivity type impurity included in the base peripheral region is lower than that included in the base region.
    • 一种半导体器件,包括:具有第一表面和第二表面的第一导电类型的半导体衬底; 形成在所述半导体衬底的所述第一表面上的所述第二导电类型的基极区域; 所述第二导电类型的保护环区域形成在所述基极区域周围,并且所述第二类型杂质的浓度低于所述基极区域的浓度; 形成在所述基底区域上的第一电极; 以及形成在所述半导体衬底的第二表面上的第二电极,还包括形成在所述基极区域周围并与所述基极区域连接的基极周边区域,其中所述基极周边区域比所述基极区域深,并且具有基本恒定的深度 ,并且包含在基础周边区域中的第二导电型杂质的浓度低于基底区域中包含的浓度。
    • 13. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US07432135B2
    • 2008-10-07
    • US11463502
    • 2006-08-09
    • Hideki Takahashi
    • Hideki Takahashi
    • H01L21/332H01L29/74H01L29/78
    • H01L29/7397H01L29/0696H01L29/0834H01L29/32H01L29/66348
    • A semiconductor device, including: a semiconductor substrate of a first conductivity type having a first and second major surfaces; a first conductivity type semiconductor layer formed on the first major surface of the semiconductor substrate; a base layer of a second conductivity type formed on the first major surface of the semiconductor layer and separated by the semiconductor layer from the semiconductor substrate; a pair of groove portions penetrating the base layer from the first major surface and reaching at least the semiconductor layer; an insulation film disposed inside the groove portion and a gate electrode formed inside the groove portion through the insulation film; a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed on the second major surface of the semiconductor substrate; and an emitter region disposed on the first major surface of the base layer and along the groove portions, wherein a transistor controlling a current flowing in the base layer by the gate electrode and a diode made of the semiconductor layer and the base layer are disposed within the semiconductor device, and the emitter region is disposed only in an area which is between the pair of groove portions.
    • 一种半导体器件,包括:具有第一和第二主表面的第一导电类型的半导体衬底; 形成在半导体衬底的第一主表面上的第一导电类型半导体层; 形成在半导体层的第一主表面上并由半导体层与半导体衬底隔开的第二导电类型的基极层; 从所述第一主表面穿透所述基底层并且至少达到所述半导体层的一对沟槽部; 设置在所述槽部内的绝缘膜和通过所述绝缘膜形成在所述槽部内的栅电极; 形成在半导体衬底的第二主表面上的第一导电类型半导体层和第二导电类型半导体层; 以及发射极区域,其设置在所述基底层的所述第一主表面上并且沿着所述沟槽部分,其中,控制由所述栅电极在所述基极层中流动的电流的晶体管和由所述半导体层和所述基极层制成的二极管设置在 半导体器件和发射极区域仅设置在一对槽部之间的区域中。
    • 17. 发明授权
    • Insulated gate transistor incorporating diode
    • 并联二极管的绝缘栅晶体管
    • US07154145B2
    • 2006-12-26
    • US10917298
    • 2004-08-13
    • Hideki Takahashi
    • Hideki Takahashi
    • H01L29/76
    • H01L29/7813H01L29/0696H01L29/1095H01L29/407H01L29/66348H01L29/7397H01L29/7803H01L29/7805H01L29/7806
    • A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the p-type base layer. The p-type base layer of each of the IGBT cells includes a flat region including an emitter region and a bottom surface penetrated by a main trench, and first and second side diffusion regions between which the flat region is interposed. The first side diffusion region is situated just above the n+-type cathode layer and each of the bottom surfaces of the side diffusion regions forms a parabola-shaped smooth curve in longitudinal section. By replacing the p+-type collector layer with the n+-type cathode layer, it is possible to apply features of the above structure to a power MOSFET.
    • 为每个IGBT单元形成像阱一样的p型基极层,并且在第一和第二类型的集电极层和n + +型阴极层上形成n + 与形成p型基底层的表面相对的表面,以便位于p型基底的正下方。 每个IGBT单元的p型基极层包括包括发射极区域和由主沟槽穿透的底表面的平坦区域,以及插入有平坦区域的第一和第二侧向扩散区域。 第一侧扩散区位于正极型阴极层正上方,并且侧扩散区的每个底表面在纵截面上形成抛物线形平滑曲线。 通过用n + SUP +型阴极层代替p + SUP +型集电极层,可以将上述结构的特征应用于功率MOSFET。