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11. 发明授权

US06363029B1 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06363029B1
公开(公告)日：2002-03-26
申请号：US09506438
申请日：2000-02-18
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit includes a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

12. 发明授权

US5086238A Semiconductor supply incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体电源，用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US5086238A
公开(公告)日：1992-02-04
申请号：US608640
申请日：1990-11-05
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , H03K17/00 , H03K19/003 , H03K19/017
CPC分类号： G11C5/147 , H03K19/00376 , H03K19/00384 , H03K19/01707 , H03K2217/0036 , Y10S323/907
摘要： A semiconductor integrated circuit includes a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the senmiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit. A control circuit provided on the semiconductor chip controls the power supply circuit, wherein the control circuit includes external power supply voltage detector and/or temperature detector and responds to the signal from the external power supply voltage detector by changing the power supply voltage to the internal circuit. Thus, the operating speed of the internal circuit is kept substantially constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的用于变换从电源端子接收用于向内部电路提供由电压变换产生的源极电压的外部电源电压。设置在半导体芯片上的控制电路控制电源电路，其中控制电路包括外部电源电压检测器和/或温度检测器，并且通过将电源电压改变为内部电压来响应来自外部电源电压检测器的信号电路。因此，内部电路的工作速度保持基本恒定。

13. 发明授权

US4730132A Semiconductor device having bipolar transistor and insulated gate field effect transistor with two potential power source 失效
标题翻译：具有双极晶体管和具有两个潜在电源的绝缘栅场效应晶体管的半导体器件
公开(公告)号：US4730132A
公开(公告)日：1988-03-08
申请号：US886816
申请日：1986-07-18
申请人： Takao Watanabe , Goro Kitukawa , Ryoichi Hori , Kiyoo Itoh , Yoshiki Kawajiri , Takayuki Kawahara
发明人： Takao Watanabe , Goro Kitukawa , Ryoichi Hori , Kiyoo Itoh , Yoshiki Kawajiri , Takayuki Kawahara
IPC分类号： G11C7/12 , G11C8/10 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/01
CPC分类号： G11C8/10 , G11C7/12 , H03K17/693 , H03K19/017 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： The invention relates to a semiconductor device which has a high density of integration and of which a low power consumption is required. The semiconductor device prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit and a succeeding circuit are provided with different reference voltages. The semiconductor device is constructed of a circuit which includes a bipolar transistor and an insulated-gate field effect transistor, and which operates with reference to one or more voltages, at least one of the reference voltages having a voltage value different from a reference operating voltage of a preceding circuit. A first switching circuit is interposed between a first reference voltage and an input node of a driver circuit, and a second switching circuit is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the seconding circuit switch is turned "on" while the first switching circuit is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switching circuit is turned "off" while the first switching circuit is turned "on". The semiconductor device is suited to high-density DRAM and SRAM circuits which use voltage limiters.

14. 发明授权

US06970391B2 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06970391B2
公开(公告)日：2005-11-29
申请号：US10441207
申请日：2003-05-20
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , G11C7/04 , G11C7/02 , G11C11/34
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

15. 发明授权

US6125075A Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
公开(公告)号：US6125075A
公开(公告)日：2000-09-26
申请号：US168998
申请日：1998-10-09
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

16. 发明授权

US5377156A Semiconductor device incorporating main and stand-by boosted internal power supply for compensating for deviation on operating condition and fabrication process conditions 失效
标题翻译：采用主要和待机增强内部电源的半导体器件，用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US5377156A
公开(公告)日：1994-12-27
申请号：US985076
申请日：1992-12-03
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

17. 发明授权

US4503522A Dynamic type semiconductor monolithic memory 失效
标题翻译：动态型半导体单片存储器
公开(公告)号：US4503522A
公开(公告)日：1985-03-05
申请号：US358678
申请日：1982-03-16
申请人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
发明人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/408 , G11C11/4096 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4085 , G11C11/4096
摘要： A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.
摘要翻译：使用MOS晶体管的动态型半导体存储器，其中分别在字驱动器之前和之后的每个级提供利用电容的第一和第二升压电路。存储器的数据线各自设置有电压补偿电路，用于将用于将存储器单元充电的电压提高到高于用于在存储器单元中重写的源电压的电平。在产生字线驱动脉冲信号之后，第一升压电路被操作。随后，字驱动器选择晶体管截止，其后是第二升压电路的操作。因此，字线电压被提升两次。

18. 发明授权

US4475181A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4475181A
公开(公告)日：1984-10-02
申请号：US337099
申请日：1982-01-05
申请人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
发明人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
IPC分类号： G11C8/00 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/408 , G11C11/418 , H03K5/135 , G11C7/00
CPC分类号： H03K5/135 , G11C11/407 , G11C11/408 , G11C11/418 , G11C8/06 , G11C8/18
摘要： A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.
摘要翻译：多路复用地址输入的半导体存储器用于通过公共外部地址线接收列地址和行地址，并且响应于第一和第二选通信号连续解码它们，从而选择一个存储单元。半导体存储器分别配备有用于列和行寻址操作的地址缓冲器，它们的输出通过公共内部地址线连续发送到列解码器和行解码器。

19. 发明授权

US06205556B1 Semiconductor integrated circuit device comprising a memory array and a processing circuit 失效
标题翻译：包括存储器阵列和处理电路的半导体集成电路器件
公开(公告)号：US06205556B1
公开(公告)日：2001-03-20
申请号：US09198658
申请日：1998-11-24
申请人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
发明人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
IPC分类号： G06F126
CPC分类号： G06N3/063
摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.
摘要翻译：这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分在平行下。此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

20. 发明授权

US5118633A Method for manufacturing a BiCMOS semiconductor device 失效
标题翻译：制造BICMOS半导体器件的方法
公开(公告)号：US5118633A
公开(公告)日：1992-06-02
申请号：US557649
申请日：1990-07-25
申请人： Kazuhiko Sagara , Kiyoo Itoh , Goro Kitsukawa , Yoshifumi Kawamoto , Yoshiki Kawajiri
发明人： Kazuhiko Sagara , Kiyoo Itoh , Goro Kitsukawa , Yoshifumi Kawamoto , Yoshiki Kawajiri
IPC分类号： H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/10817 , Y10S148/144
摘要： Sources and drains of MOS transistors are formed after the formation of an emitter of a bipolar transistor, whereby the sources and drains are made smaller in thickness than the emitter. Since the sources and drains are not subjected to a high-temperature heat treatment conducted in the formation of the emitter, there is no fear of increase in thickness of the sources and drains caused by the diffusion of impurities. There can be formed a BiCMOS having a high integration density and superior characteristics.

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