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    • 11. 发明申请
    • PLL Circuit, phase shifting method, and IC chip
    • PLL电路,相移方法和IC芯片
    • US20080157868A1
    • 2008-07-03
    • US11980389
    • 2007-10-31
    • Masato Kita
    • Masato Kita
    • H03D3/00
    • H03D3/241H03D3/007
    • A PLL circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by π/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal, and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal, based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.
    • PLL电路包括:时钟信号发生单元,用于产生第一时钟信号和第二时钟信号,其中该相位与第一时钟信号不同于pi / 2; 用于计算第一相位比较结果的计算单元,其示出将第一时钟信号经过相移的信号与PSK调制信号进行比较的结果,以及示出比较信号的相位的结果的第二相位比较结果 其中所述第二时钟信号基于所述第一和第二参数,所述第一时钟信号,所述第二时钟信号和所述PSK调制信号,利用所述PSK调制信号进行相移; 用于虚拟地控制所述控制角的控制方向设定单元; 参数控制单元; 以及读取控制单元,用于控制从PSK调制读取数据的定时。