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11. 发明授权

US07902025B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07902025B2
公开(公告)日：2011-03-08
申请号：US11773649
申请日：2007-07-05
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
摘要翻译：制备由半导体材料制成的半导体衬底，并且在半导体衬底上形成异质半导体区域，以在异质半导体区域和半导体衬底之间的界面中形成异质结。异质半导体区域由具有与半导体材料的带隙不同的带隙的半导体材料制成，并且异质半导体区域的一部分包括膜厚度比其他部分薄的膜厚控制部分。通过以等于膜厚控制部分的膜厚的厚度氧化杂半导体区域，形成与异质结相邻的栅极绝缘膜。在栅极绝缘膜上形成栅电极。这使得可以制造包括具有较低导通电阻的栅极绝缘膜以及更高的绝缘特性和可靠性的半导体器件。

12. 发明授权

US07588961B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07588961B2
公开(公告)日：2009-09-15
申请号：US11377909
申请日：2006-03-16
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/00
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.
摘要翻译：通常，本公开描述了在反向偏置状态下呈现增加的电阻和减小的漏电流的半导体器件，以及用于制造这种半导体器件的方法。例如，在一个实施例中，通过在形成在N型外延层上的多晶硅层中引入P +或P-型杂质来获得反向偏置状态下的增加的电阻。此外，半导体器件在正向偏置状态下保持低电阻。为了使正向偏置电阻低，在栅电极附近的多晶硅层可以是N +型。此外，在多晶硅层的表面上形成N +型源极提取区域，以将源电极连接到漏电极，并且当正向偏置时保持低电阻。

13. 发明申请

US20070235745A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235745A1
公开(公告)日：2007-10-11
申请号：US11783577
申请日：2007-04-10
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L33/00 , H01L29/861 , H01L29/80
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/1608 , H01L29/165 , H01L29/6606 , H01L29/7802 , H01L29/7811 , H01L29/7828 , H01L29/8083 , H01L29/861 , H01L29/8618 , H01L29/872
摘要： Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
摘要翻译：设定第二半导体区域的杂质浓度，使得当将预定的反向偏压施加到由第一半导体区域和第二半导体区域构成的异质结二极管时，至少在异种结区以外的击穿电压异质结二极管是半导体器件的击穿电压。

14. 发明申请

US20070210330A1 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070210330A1
公开(公告)日：2007-09-13
申请号：US11714214
申请日：2007-03-06
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/732 , H01L21/8234
CPC分类号： H01L29/267 , H01L21/0475 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
摘要翻译：一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

15. 发明授权

US07989295B2 Method of manufacturing semiconductor device 有权
公开(公告)号：US07989295B2
公开(公告)日：2011-08-02
申请号：US13014190
申请日：2011-01-26
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.

16. 发明授权

US07671383B2 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07671383B2
公开(公告)日：2010-03-02
申请号：US11714214
申请日：2007-03-06
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/732
CPC分类号： H01L29/267 , H01L21/0475 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
摘要翻译：一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

17. 发明申请

US20090278169A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090278169A1
公开(公告)日：2009-11-12
申请号：US12065847
申请日：2006-08-22
申请人： Tetsuya Hayashi , Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/861 , H01L21/046 , H01L29/0623 , H01L29/0653 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.
摘要翻译：半导体器件包括：半导体基底; 与半导体基底接触并且具有与半导体基底不同的带隙的异质半导体区域; 连接到所述异质半导体区域的第一电极; 以及形成与半导体基底的欧姆接触的第二电极。异质半导体区域包括通过层叠在至少两层之间的边界处晶体取向不连续的多个半导体层而形成的层叠异质半导体区域。

18. 发明授权

US07531396B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07531396B2
公开(公告)日：2009-05-12
申请号：US11374418
申请日：2006-03-14
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/338 , H01L21/066
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译：公开了制造半导体器件的方法。半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极异质半导体区域和半导体本体通过栅极绝缘膜。该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

19. 发明申请

US20070252173A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070252173A1
公开(公告)日：2007-11-01
申请号：US11790791
申请日：2007-04-27
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/739
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/4916 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.
摘要翻译：半导体器件具有：预定的导电型的半导体衬底; 与所述半导体衬底的第一主表面接触并且包括具有与所述半导体衬底的带隙不同的带隙的半导体材料的异质半导体区域; 在与所述异质半导体区域和所述半导体基板之间的接合区域相邻的位置处形成的栅极电极，连接到所述异质半导体区的源电极; 和连接到半导体衬底的漏电极; 其中所述异质半导体区域包括与所述源电极接触的接触部分，所述接触部分的至少一部分区域具有与所述半导体衬底的导电型相同的导电类型，并且所述部分区域的杂质浓度高于至少通过栅极绝缘体层位于面向栅电极的异质半导体区域中的栅电极面对部分的部分区域的杂质浓度。

20. 发明申请

US20070252171A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252171A1
公开(公告)日：2007-11-01
申请号：US11790679
申请日：2007-04-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L29/732
CPC分类号： H01L29/8613 , H01L21/0465 , H01L21/0475 , H01L29/0615 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66136
摘要： As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.
摘要翻译：作为与通过在与阴极连接的N +碳化硅衬底上形成N-碳化硅外延层而构成的半导体衬底的第一主表面接触的半导体区域，提供了具有相同导电性的N +多晶硅层类型为半导体基底的导电类型和不同于半导体基底的导电类型的导电类型的P +多晶硅层。 N +多晶硅层和P +多晶硅层都与半导体基体异相接合，并与欧姆连接到阳极电极。此外，形成与半导体基底的导电类型相同的导电类型的N +多晶硅层，以便与半导体基底的第一主表面接触，并且与导电类型不同的导电类型的P +多晶硅层形成在半导体基底的第一主表面上的沟槽中。

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