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11. 发明授权

US5159598A Buffer integrated circuit providing testing interface 失效
标题翻译：缓冲器集成电路提供测试接口
公开(公告)号：US5159598A
公开(公告)日：1992-10-27
申请号：US518589
申请日：1990-05-03
申请人： Kenneth B. Welles, II , Paul A. Delano , Richard I. Hartley , Michael J. Hartman , Abhijit Chatterjee
发明人： Kenneth B. Welles, II , Paul A. Delano , Richard I. Hartley , Michael J. Hartman , Abhijit Chatterjee
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/00 , G06F11/18 , G06F11/22
CPC分类号： G01R31/318533 , G06F11/183 , G06F11/187
摘要： An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.
摘要翻译：辅助单片集成电路芯片提供缓冲放大和测试接口。现有的单片集成电路芯片可以在每个输入端口之间和每个输出端口之后使用这些辅助缓冲器芯片之一连接到电子系统中，以实现与内置的单片集成电路芯片上类似的功能测试测试电路。

12. 发明授权

US5115437A Internal test circuitry for integrated circuits using token passing to select testing ports 失效
标题翻译：内部测试电路，用于使用令牌传递来选择测试端口的集成电路
公开(公告)号：US5115437A
公开(公告)日：1992-05-19
申请号：US487481
申请日：1990-03-02
申请人： Kenneth B. Welles, II , Richard I. Hartley , Michael J. Hartman
发明人： Kenneth B. Welles, II , Richard I. Hartley , Michael J. Hartman
IPC分类号： G01R31/3185
CPC分类号： G01R31/318561
摘要： Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied.
摘要翻译：内置测试电路，适用于要连接在多芯片封装中的单片集成电路芯片，使用电子令牌传递来选择要测试的电路中的一个测试输入端口，以应用测试输入向量。内置测试电路还使用电子令牌传递来选择要供应的测试结果的待测电路中的一个测试输出端口。

13. 发明授权

US4860240A Low-latency two's complement bit-serial multiplier 失效
标题翻译：低延迟二进制补码位串行乘法器
公开(公告)号：US4860240A
公开(公告)日：1989-08-22
申请号：US134271
申请日：1987-12-14
申请人： Richard I. Hartley , Peter F. Corbett
发明人： Richard I. Hartley , Peter F. Corbett
IPC分类号： G06F7/52
CPC分类号： G06F7/525 , G06F2207/3896
摘要： A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.
摘要翻译：双精度，低延迟二进制补码位串行乘法器的作用在于，在两个输入都被完全读入乘法器之后，计算已经进行到可以用单个计数器完成的阶段。乘法器包括串联连接的多个位片和端单元。操作数的串行比特流由每个比特片中的锁存器进行采样，并且使用（5,3）个计数器累加采样比特值以产生部分和输出信号。最后一位片段的部分和输出信号是双精度积的最低有效字。端单元包括另一个（5,3）计数器，其累积传播和并携带位片的输出信号并产生双精度乘积的最高有效字。

14. 发明授权

US5187754A Forming, with the aid of an overview image, a composite image from a mosaic of images 失效
标题翻译：通过概览图像形成来自马赛克图像的合成图像
公开(公告)号：US5187754A
公开(公告)日：1993-02-16
申请号：US693461
申请日：1991-04-30
申请人： Bena L. Currin , Aiman A. Abdel-Malek , Richard I. Hartley
发明人： Bena L. Currin , Aiman A. Abdel-Malek , Richard I. Hartley
IPC分类号： G09B9/30 , G06T1/00 , G06T3/00 , G06T3/40 , G06T15/20 , H04N7/26
CPC分类号： G06T3/4007 , G06K9/0063 , G06K9/32 , G06T15/205 , G06T3/4038 , H04N19/23 , G06K2009/2045
摘要： A method for generating a composite terrain map, proceeding from an overview taken at relatively high altitude and photographs taken at relatively low altitudes, generates a composite terrain map that is relatively free of step irradiance variations where the photographs taken at relatively low altitudes are splined. Digitized representations of orthographic projections of the overview and each of the lower-altitude photographs, as regularly sampled in two orthogonal dimensions and referred to a common spatial frame of reference, are generated. The digitized representations of the orthographic projections of each of said photographs taken at relatively low altitudes are hig-pass spatially filtered, to generate digitized high-spatial-frequency responses. The digitized high-spatial-frequency responses are splined to generate a digitized high-spatial-frequency response for the composite terrain map. This digitized high-spatial-frequency response is merged with a digitized low-spatial-frequency response for the composite terrain map obtained by low-pass spatially filtering the digitized representations of the orthographic projection of the overview.
摘要翻译：从在较高高度拍摄的概览和在较低高度拍摄的照片进行的生成复合地形图的方法产生相对没有步进辐照度变化的复合地形图，其中在相对低的高度拍摄的照片是花键的。产生概述和每个低空照片的正交投影的数字化表示，如在两个正交维度上定期采样并被称为公共空间参照系。在相对较低的高度拍摄的每张照片的正投影的数字化表示被高通空间滤波，以产生数字化的高空间频率响应。数字化的高空间频率响应被拼接以产生用于复合地形图的数字化高空间频率响应。该数字化的高空间频率响应与通过对概述的正投影的数字化表示的低通空间滤波获得的复合地形图的数字化低空间频率响应进行合并。

15. 发明授权

US5177691A Measuring velocity of a target by Doppler shift, using improvements in calculating discrete Fourier transform 失效
标题翻译：通过多普勒频移测量目标的速度，使用计算离散傅立叶变换的改进
公开(公告)号：US5177691A
公开(公告)日：1993-01-05
申请号：US620511
申请日：1990-11-30
申请人： Kenneth B. Welles , Richard I. Hartley
发明人： Kenneth B. Welles , Richard I. Hartley
IPC分类号： G01P5/24 , G01R23/167 , G01S15/58 , G06F17/14
CPC分类号： G01P5/241 , G01R23/167 , G01S15/58 , G06F17/141
摘要： The invention is embodied in improvements in calculating discrete Fourier transform (DFT) using recursive digital filtering in a method for determining the velocity of a target located in a medium for vibratory energy. In the method a transmitter electrical signal of prescribed frequency is generated. Coherent vibratory energy, the frequency of which is in fixed relationship with said prescribed frequency, is transmitted into the medium and is directed toward the target. The transmitting is done in recurring pulses of prescribed duration. During range gate intervals each of prescribed duration, the transmitted coherent vibratory energy is received from the medium after its interaction with the target. The vibratory energy which is received during the range gate intervals is converted to a receiver electrical signal. The transmitter and receiver electrical signals are mixed together to obtain a demodulated electrical signal through heterodyning or homodyning. The demodulated electrical signal is digitized and then digitally filtered on a recursive basis to separate it into digitized spectral components in accordance with a discrete Fourier transform procedure. Squaring the absolute value of each of the digitized spectral components generates digital electric signals descriptive of the power spectrum of the interaction of the vibratory energy with said target. After performing a comparative analysis of the digital electric signals descriptive of that power spectrum, the velocity of the target is calculated from the results of the comparative analysis.
摘要翻译：本发明体现在使用递归数字滤波来计算离散傅立叶变换（DFT）的改进，该方法用于确定位于用于振动能的介质中的目标的速度。在该方法中，产生规定频率的发射机电信号。其频率与所述规定频率处于固定关系的相干振动能量被传送到介质中并被指向目标。发射以规定持续时间的循环脉冲完成。在每个规定持续时间的范围门间隔期间，在与目标相互作用之后从介质接收所发射的相干振动能。在范围门间隔期间接收的振动能量被转换为接收器电信号。将发射机和接收机电信号混合在一起，以通过外差或并联获得解调的电信号。解调的电信号被数字化，然后在递归的基础上进行数字滤波，以便根据离散傅立叶变换程序将其分离成数字化的频谱分量。平衡每个数字化频谱分量的绝对值产生描述振动能与所述目标的相互作用的功率谱的数字电信号。在对该功率谱描述的数字电信号进行比较分析之后，根据比较分析的结果计算目标的速度。

16. 发明授权

US5175843A Computer-aided design method for restructuring computational networks to minimize shimming delays 失效
标题翻译：用于重组计算网络的计算机辅助设计方法，以最小化匀场延迟
公开(公告)号：US5175843A
公开(公告)日：1992-12-29
申请号：US428808
申请日：1989-10-30
申请人： Albert E. Casavant , Richard I. Hartley
发明人： Albert E. Casavant , Richard I. Hartley
IPC分类号： G06F7/00 , G06F17/50
CPC分类号： G06F17/5045 , G06F7/00
摘要： A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and commutative combining of its respective imput operands to generate a respective output operand, are converted to data-flow graphs with multiple-input operators. Data-flow graphs with multiple-input operators, after being optimally scheduled, are converted to data-flow graphs which use trees of dual-input operators or of dual-input and three-input operators, those trees having minimum latency and shim delay associated with them. These data-flow graphs then have shim delay minimized in them, e.g. by being subjected to linear programming.
摘要翻译：一种计算机辅助设计方法，用于重组计算网络以最小化等待时间和垫片延迟，适用于硅编译器。使用运算树的计算网络的数据流图转换为具有多输入运算符的数据流图，每个运算符执行相应的输入运算的相关和交换组合以产生相应的输出操作数。具有多输入运算符的数据流图在经过优化调度后，转换为使用双输入运算符或双输入和三输入运算符树的数据流图，这些树具有最小的延迟和相关的延迟延迟跟他们。这些数据流图在其中具有最小化的垫片延迟，例如。通过进行线性规划。

17. 发明授权

US5010511A Digit-serial linear combining apparatus useful in dividers 失效
标题翻译：用于分频器的数字串行线性组合装置
公开(公告)号：US5010511A
公开(公告)日：1991-04-23
申请号：US265210
申请日：1988-10-31
申请人： Richard I. Hartley , Peter F. Corbett
发明人： Richard I. Hartley , Peter F. Corbett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions. The capability of performing addition or subtraction as the result of comparison permits non-restoring division to be done using a plurality of the linear combining apparatuses.
摘要翻译：数字串行数据线性组合装置执行加，减和比较功能。作为比较结果执行加法或减法的能力允许使用多个线性组合装置进行非恢复划分。

18. 发明授权

US5396531A Method of achieving reduced dose X-ray fluoroscopy by employing statistical estimation of poisson noise 失效
标题翻译：通过使用泊松噪声的统计估计来实现减少剂量X射线荧光透视的方法
公开(公告)号：US5396531A
公开(公告)日：1995-03-07
申请号：US971652
申请日：1992-11-05
申请人： Richard I. Hartley
发明人： Richard I. Hartley
IPC分类号： G06K9/40 , H04N5/32 , H05G1/32 , H05G1/46 , H05G1/60
CPC分类号： G06K9/40 , H04N5/32 , H05G1/32 , H05G1/46 , H05G1/60
摘要： An interactive system for producing X-ray fluoroscopic images determines X-ray tube photon count and voltage for producing acceptable quality images while minimizing X-ray radiation dosage to a subject. An image is created and a signal to noise (S/N) ratio is estimated from the image, assuming a Poisson model is assumed for the X-ray image. The S/N ratio is determined by solving several simultaneous equations and the photon count is estimated to produce an image with a desired S/N ratio. Subsequent X-ray fluoroscopy images are produced with the optimum photon count Q, thereby reducing X-ray dosage. The optimization is repeated periodically to readjust the system.
摘要翻译：用于产生X射线透视图像的交互式系统确定用于产生可接受质量图像的X射线管光子计数和电压，同时使对受试者的X射线辐射剂量最小化。假设为X射线图像假设泊松模型，则从图像中产生图像并估计信噪比（S / N）比。通过求解几个联立方程来确定S / N比，并且估计光子计数以产生具有所需S / N比的图像。随后用最佳光子计数Q产生X射线透视图像，从而减少X射线剂量。定期重复优化以重新调整系统。

19. 发明授权

US5034909A Digit-serial recursive filters 失效
标题翻译：数字串行递归滤波器
公开(公告)号：US5034909A
公开(公告)日：1991-07-23
申请号：US486632
申请日：1990-02-28
申请人： Richard I. Hartley
发明人： Richard I. Hartley
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： A recursive digital filter for digit-serial signals comprises a digit-serial adder having an augend input port to which successions of m-bit-wide digits of a digital-serial filter input signal are supplied in order of progressively greater significance, having at least a first addend input port, and having a sum output port; digit-serial multiplier apparatus having a multiplicand input port connected from the sum output port of said digit-serial adder and having a product output port for supplying a weighted response to signal received at its multiplicand input port; and means for applying the weighted response to the first addend input port of the digit-serial adder so as to be in word alignment with the digit-serial input signal to the augend input port of the digit-serial adder. In various filtering systems the recursive digital filter for digit-serial signals is preceded by a to-digit-serial converter to convert digit-serial format input signal supplied in a different digital signal format, is succeeded by a from-digit-serial converter to convert the digit-serial filter response to a different digital signal format, or is both preceded by a to-digit-serial converter and succeeded by a from-digit-serial converter.
摘要翻译：用于数字串行信号的递归数字滤波器包括具有加法输入端口的数字串行加法器，数字串行滤波器输入信号的m位宽位数的相继以逐渐更大的重要性提供顺序，至少具有第一加数输入端口，并具有和输出端口; 数字串行乘法器具有从所述数字串行加法器的和输出端口连接的被乘数输入端口，并具有产品输出端口，用于向在其被乘数输入端口接收的信号提供加权响应; 以及用于将数字串行加法器的第一加数输入端口加权的响应应用于与数字串行加法器的加法输入端口的数字串行输入信号字对齐的装置。在各种滤波系统中，用于数字串行信号的递归数字滤波器之前是一个数位串行转换器，用于转换以不同数字信号格式提供的数字串行格式输入信号，由数位串行转换器将数字串行滤波器响应转换为不同的数字信号格式，或者先于数字串行转换器，并由数位串行转换器成功。

20. 发明授权

US5025257A Increased performance of digital integrated circuits by processing with multiple-bit-width digits 失效
公开(公告)号：US5025257A
公开(公告)日：1991-06-18
申请号：US482122
申请日：1990-02-20
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

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