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11. 发明授权

US08686985B2 Active liquid crystal display drivers and duty cycle operation 有权
标题翻译：主动液晶显示驱动器和占空比操作
公开(公告)号：US08686985B2
公开(公告)日：2014-04-01
申请号：US11965520
申请日：2007-12-27
申请人： Warren Snyder , Harold Kutz , Timothy Williams , Bert Sullam , David Wright
发明人： Warren Snyder , Harold Kutz , Timothy Williams , Bert Sullam , David Wright
IPC分类号： G09G5/00
CPC分类号： H03K17/687 , H03K19/0016 , H03K19/00369
摘要： A liquid crystal display (LCD) driving system includes a reference voltage generator to generate a plurality of reference voltages. The LCD driving system also includes a plurality of drive buffers to generate drive voltages according to at least one of the reference voltages, and to drive at least a portion of a liquid crystal display to present data according to the drive voltages.
摘要翻译：液晶显示器（LCD）驱动系统包括用于产生多个参考电压的参考电压发生器。 LCD驱动系统还包括多个驱动缓冲器，以根据至少一个参考电压产生驱动电压，并且驱动至少一部分液晶显示器以根据驱动电压呈现数据。

12. 发明授权

US07479913B1 Configurable analog to digital converter 有权
标题翻译：可配置的模数转换器
公开(公告)号：US07479913B1
公开(公告)日：2009-01-20
申请号：US11703873
申请日：2007-02-07
申请人： Eashwar Thiagarajan , Bert Sullam
发明人： Eashwar Thiagarajan , Bert Sullam
IPC分类号： H03M1/12
CPC分类号： H03M1/005 , H03M1/007 , H03M1/52 , H03M3/394 , H03M3/398 , H03M3/414
摘要： A configurable analog to digital converter (ADC) includes a plurality of analog units to integrate an input signal. The analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal and are further coupled to a plurality of bus segments via a plurality of interconnect circuits. Each interconnect circuit is configured to selectively couple the analog units to any of the bus segments.
摘要翻译：可配置的模数转换器（ADC）包括多个模拟单元以集成输入信号。模拟单元耦合在一起以响应于输入信号产生多个离散时间信号，并且还经由多个互连电路耦合到多个总线段。每个互连电路被配置为选择性地将模拟单元耦合到任何总线段。

13. 发明授权

US06614320B1 System and method of providing a programmable clock architecture for an advanced microcontroller 有权
标题翻译：为高级微控制器提供可编程时钟架构的系统和方法
公开(公告)号：US06614320B1
公开(公告)日：2003-09-02
申请号：US10000383
申请日：2001-10-24
申请人： Bert Sullam , Harold Kutz
发明人： Bert Sullam , Harold Kutz
IPC分类号： H03B2800
CPC分类号： G06F1/32 , G06F1/06 , G06F1/08
摘要： One embodiment of the present invention is a programmable clock architecture for a microcontroller that provides multiple different clocking signal frequencies that may be utilized by one or more programmable logic blocks of the microcontroller. In this manner, the clocking architecture enables the programmable logic blocks to perform a wider variety of functions because they have access to a wider variety of clock signal frequencies. Specifically, the clocking architecture of the present embodiment includes a plurality of clocking sources. For example, the output clocking signal of one of the clock oscillators is divided down to different smaller frequencies and also multiplied to provide more frequencies that may be utilized by the programmable circuit blocks and processor of the microcontroller. Additionally, the clocking architecture includes a programmable option of utilizing precision clocking signals and/or less precise clocking signals depending on the desired applications of the microcontroller's programmable circuit blocks.
摘要翻译：本发明的一个实施例是用于微控制器的可编程时钟架构，其提供可由微控制器的一个或多个可编程逻辑块利用的多个不同的时钟信号频率。以这种方式，时钟架构使得可编程逻辑块能够执行更多种功能，因为它们可以访问更多种类的时钟信号频率。具体地，本实施例的时钟体系结构包括多个时钟源。例如，其中一个时钟振荡器的输出时钟信号被分成不同的较小频率，并且相乘以提供可被微控制器的可编程电路块和处理器利用的更多频率。此外，时钟架构包括根据微控制器的可编程电路块的期望应用利用精确时钟信号和/或更精确的时钟信号的可编程选项。

14. 发明授权

US08250249B1 Processor independent line driving and receiving system 有权
标题翻译：处理器独立线路驱动和接收系统
公开(公告)号：US08250249B1
公开(公告)日：2012-08-21
申请号：US12509394
申请日：2009-07-24
申请人： Gaurang Kavaiya , Rick Harding , Mark Ainsworth , Bert Sullam
发明人： Gaurang Kavaiya , Rick Harding , Mark Ainsworth , Bert Sullam
IPC分类号： G06F3/00
CPC分类号： G06F13/4072 , H04L25/0272 , H04L25/028 , H04L25/0292
摘要： A programmable system includes a core processing unit to perform various data operations. The programmable system includes a transceiver having programmable analog and digital devices that, when initially configured by the programmable system, receive and collect status information of other programmable systems independently of the data operations performed by the core processing unit.
摘要翻译：可编程系统包括执行各种数据操作的核心处理单元。该可编程系统包括具有可编程模拟和数字装置的收发器，当最初由可编程系统配置时，它可以独立于核心处理单元进行的数据操作来接收和收集其他可编程系统的状态信息。

15. 发明申请

US20080259698A1 HIGH SPEED DUAL PORT MEMORY WITHOUT SENSE AMPLIFIER 审中-公开
标题翻译：高速双端口存储器，无感测放大器
公开(公告)号：US20080259698A1
公开(公告)日：2008-10-23
申请号：US11967243
申请日：2007-12-30
申请人： Onur Ozbek , Bert Sullam
发明人： Onur Ozbek , Bert Sullam
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/16 , G11C8/08 , G11C8/14 , G11C11/412 , H03K17/6872
摘要： A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell to store data received over one or more write bit lines, and a sensing inversion device coupled to the memory cell and word lines. The sensing inversion device can read data stored by the memory cell and provide the read data to one or more read bit lines when at least one of the word lines is activated for read operations.
摘要翻译：系统包括至少一个字线解码器以选择要激活的字线，以及具有多个存储单元装置的存储单元阵列，用于存储通过一个或多个写位线接收的数据。存储单元装置中的至少一个包括用于存储在一个或多个写位线上接收的数据的存储单元，以及耦合到存储单元和字线的感测反相装置。当至少一个字线被激活用于读取操作时，感测反转装置可以读取由存储器单元存储的数据并将读取的数据提供给一个或多个读取位线。

16. 发明授权

US08639850B1 Addressing scheme to allow flexible mapping of functions in a programmable logic array 有权
标题翻译：寻址方案允许在可编程逻辑阵列中灵活地映射功能
公开(公告)号：US08639850B1
公开(公告)日：2014-01-28
申请号：US13364629
申请日：2012-02-02
申请人： Bert Sullam
发明人： Bert Sullam
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F12/06 , G06F12/109
摘要： A method for implementing an addressing scheme may include mapping a digital peripheral function to one or more contiguous configurable blocks in an array of configurable blocks; and assigning a memory address from a plurality of memory addresses to at least one register of each of the one or more contiguous configurable blocks based on an access mode width of the digital peripheral function and a width of each of the one or more contiguous configurable blocks.
摘要翻译：用于实现寻址方案的方法可以包括将数字外围功能映射到可配置块的阵列中的一个或多个连续可配置块; 以及基于所述数字外围功能的访问模式宽度和所述一个或多个相邻可配置块中的每一个的宽度，将存储器地址从多个存储器地址分配给所述一个或多个相邻可配置块中的每一个的至少一个寄存器。

17. 发明授权

US08402313B1 Reconfigurable testing system and method 有权
标题翻译：可重构测试系统和方法
公开(公告)号：US08402313B1
公开(公告)日：2013-03-19
申请号：US11986338
申请日：2007-11-20
申请人： Matthew A. Pleis , Bert Sullam , Todd Lesher
发明人： Matthew A. Pleis , Bert Sullam , Todd Lesher
IPC分类号： G06F11/00
CPC分类号： G06F11/273
摘要： One disclosed system and method enables dynamic reconfiguration of an electronic device in association with testing activities in a convenient and efficient manner. In one implementation, the electronic device includes a bus for communicating information, a microprocessor for processing data, a programmable functional component including a plurality of functional blocks programmable to provide a plurality of functions and configurations, and a memory for storing instructions including instructions for causing the programmable functional component to change functions and configurations. The components are programmably configurable to perform a variety of functions. In one example, the memory stores a plurality of configuration images that define the configuration and functionality of the circuit. The information stored in the memory facilitates dynamic reconfiguration of the circuit in accordance with the test harness instructions. Based upon a command from a test computer, the electronic device is automatically reconfigured by the test harness activating different configuration images.
摘要翻译：一种公开的系统和方法能够以方便和有效的方式与测试活动相关联地进行电子设备的动态重新配置。在一个实现中，电子设备包括用于传送信息的总线，用于处理数据的微处理器，包括可编程以提供多个功能和配置的多个功能块的可编程功能组件，以及用于存储包括用于引起可编程功能组件来改变功能和配置。这些组件可编程配置以执行各种功能。在一个示例中，存储器存储定义电路的配置和功能的多个配置图像。存储在存储器中的信息有助于根据测试线束指令对电路的动态重新配置。基于来自测试计算机的命令，电子设备由激活不同配置图像的测试线束自动重新配置。

18. 发明授权

US08026739B2 System level interconnect with programmable switching 有权
标题翻译：系统级互连与可编程切换
公开(公告)号：US08026739B2
公开(公告)日：2011-09-27
申请号：US11965677
申请日：2007-12-27
申请人： Bert Sullam , Warren Snyder , Haneef Mohammed
发明人： Bert Sullam , Warren Snyder , Haneef Mohammed
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/173 , H03K19/177 , H03K19/17704 , H03K19/1776
摘要： Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.
摘要翻译：不同的功能元件都位于相同的集成电路中，其中至少一个功能元件包括微控制器。集成电路中的配置寄存器或配置存储器存储由微控制器加载的配置值。连接器配置为将集成电路连接到外部信号。位于集成电路中的系统级互连可根据加载到配置寄存器中的配置值可编程地将不同功能元件和不同连接器连接在一起。

19. 发明申请

US20080288755A1 CLOCK DRIVEN DYNAMIC DATAPATH CHAINING 有权
标题翻译：时钟驱动动态数据链
公开(公告)号：US20080288755A1
公开(公告)日：2008-11-20
申请号：US12104391
申请日：2008-04-16
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F9/302
CPC分类号： H03K19/17728
摘要： A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.
摘要翻译：系统包括多个数据路径，每个数据路径具有至少部分地基于配置数据执行各种算术运算的结构运算元件。该系统还包括耦合到数据路径的配置存储器，配置存储器，用于向数据路径提供配置数据，这导致数据路径在执行算术运算时进行协作。

20. 发明申请

US20080258759A1 UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING 有权
标题翻译：通用数字块互连和通道路由
公开(公告)号：US20080258759A1
公开(公告)日：2008-10-23
申请号：US11965291
申请日：2007-12-27
申请人： Warren Snyder , Bert Sullam , Haneef Mohammed
发明人： Warren Snyder , Bert Sullam , Haneef Mohammed
IPC分类号： H03K19/173
CPC分类号： G06F13/28 , G06F13/4009 , H03K19/177
摘要： A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.
摘要翻译：可编程路由方案提供通用数字模块（UDB）之间以及UDB与其他微控制器元件，外设和同一集成电路（IC）中的外部输入和输出（I / O）之间的改进连接。路由方案增加了可编程架构的功能数量，灵活性和总体布线效率。 UDB可以成对分组并共享相关的水平路由信道。双向水平和垂直分割元素在不同的UDB对之间和其他外围设备和I / O之间水平和垂直扩展路由。

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