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11. 发明授权

US08213548B2 Methods and apparatus for dynamic packet reordering 有权
标题翻译：动态数据包重新排序的方法和装置
公开(公告)号：US08213548B2
公开(公告)日：2012-07-03
申请号：US11398205
申请日：2006-04-04
申请人： Jinxia Bai , Chinnappa K. Ganapathy , Thomas Sun
发明人： Jinxia Bai , Chinnappa K. Ganapathy , Thomas Sun
IPC分类号： H04L27/28 , H04L27/00 , H04L27/06 , H04K1/10
CPC分类号： H04L27/2647 , H04L1/0045 , H04L1/0066 , H04L1/007 , H04L25/067
摘要： Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.
摘要翻译：动态数据包重新排序的方法和装置。在一方面，提供了一种用于在运行中处理时隙数据以产生可解码分组的方法，其中时隙数据包括交织的调制符号。该方法包括对交织的调制符号的流进行解交织以产生调制符号流，基于调制符号流计算LLR度量的并行流，以及映射LLR度量的并行流以产生可解码分组流。在另一方面，提供了一种装置，其包括解交织逻辑以对交织的调制符号流进行解交织以产生调制符号流，度量处理逻辑被配置为基于调制符号流产生并行的LLR度量流以及配置成映射LLR度量的并行流的映射逻辑以产生可解码分组流。

12. 发明授权

US07702712B2 FFT architecture and method 失效
标题翻译： FFT架构和方法
公开(公告)号：US07702712B2
公开(公告)日：2010-04-20
申请号：US11002478
申请日：2004-12-01
申请人： Raghuraman Krishnamoorthi , Chinnappa K. Ganapathy
发明人： Raghuraman Krishnamoorthi , Chinnappa K. Ganapathy
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L27/265
摘要： A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0
摘要翻译：快速傅里叶变换（FFT）硬件实现和方法提供了有效的FFT处理，同时最小化集成电路（IC）所需的管芯面积。 FFT硬件可以实现N点FFT，其中N = rn是基数（r）的函数。硬件实现包括具有N / r行的采样存储器，每个存储r个样本。旋转因子存储器可以存储每行的k个旋转因子，其中0

13. 发明授权

US07529531B2 Apparatus and methods for estimating a sleep clock frequency 失效
标题翻译：用于估计睡眠时钟频率的装置和方法
公开(公告)号：US07529531B2
公开(公告)日：2009-05-05
申请号：US11271445
申请日：2005-11-09
申请人： Michael Mao Wang , Chinnappa K. Ganapathy , Jinxia Bai
发明人： Michael Mao Wang , Chinnappa K. Ganapathy , Jinxia Bai
IPC分类号： H04B14/02
CPC分类号： H04W52/029 , Y02D70/166
摘要： Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.
摘要翻译：使用诸如温度补偿晶体振荡器的快速时钟来估计睡眠或慢时钟频率的装置和方法。所公开的装置包括具有第一计数器的估计器，该第一计数器接收发出睡眠时钟周期的每个周期的休眠时钟同步脉冲，但是与快速时钟同步。慢时钟同步脉冲被计数到预定数量; 然后发出完整计数信号。第二计数器接收完全计数信号，并且每当接收到全计数信号时递增。第三个计数器计数快速时钟周期，直到发生完全计数信号。基于慢速和快速时钟周期的计数次数，可以仅使用用于执行测量的快速时钟的域来确定慢时钟的频率，从而将测量的精度与快速时钟的精度相结合。所公开的装置还包括采用所公开的估计器的集成电路和收发器。还公开了相应的方法。

14. 发明授权

US08612693B2 Optimized transfer of packets in a resource constrained operating environment 有权
标题翻译：在资源受限的操作环境中优化数据包的传输
公开(公告)号：US08612693B2
公开(公告)日：2013-12-17
申请号：US12573660
申请日：2009-10-05
申请人： Gregory K. Woods , Chinnappa K. Ganapathy , James William Dolter , Vito R. Bica , Jared S. Grubb
发明人： Gregory K. Woods , Chinnappa K. Ganapathy , James William Dolter , Vito R. Bica , Jared S. Grubb
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/00
摘要： An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory.
摘要翻译：一种装置包括第一和第二组件，存储器和分配器，其被配置为将所述存储器的一部分分配给所述第一组件，其中所述第一组件被配置为访问所述存储器的所分配的部分并将信息发送到所述第二组件提供第二组件对存储器的分配部分的访问。

15. 发明授权

US08543629B2 IFFT processing in wireless communications 有权
标题翻译：无线通信中的IFFT处理
公开(公告)号：US08543629B2
公开(公告)日：2013-09-24
申请号：US11612455
申请日：2006-12-18
申请人： Jai N. Subrahmanyam , Chinnappa K. Ganapathy , Durk L. Van Veen , Jinxia Bai , Kevin S. Cousineau , Seokyong Oh
发明人： Jai N. Subrahmanyam , Chinnappa K. Ganapathy , Durk L. Van Veen , Jinxia Bai , Kevin S. Cousineau , Seokyong Oh
IPC分类号： G06F17/14
CPC分类号： H04L27/2626
摘要： Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.
摘要翻译：描述了用于穿孔IFFT流水线的技术。在一些方面，流水线通过具有具有第一，第二和第三部分的存储器的处理系统来实现，编码器被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的数据，IFFT被配置以循环方式处理第一，第二和第三部分中的每一个中的编码数据，以及后处理器，其被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的经IFFT处理的数据。

16. 发明申请

US20100241816A1 OPTIMIZED TRANSFER OF PACKETS IN A RESOURCE CONSTRAINED OPERATING ENVIRONMENT 有权
标题翻译：资源约束作业环境中的优化包装转移
公开(公告)号：US20100241816A1
公开(公告)日：2010-09-23
申请号：US12573660
申请日：2009-10-05
申请人： Gregory K. Woods , Chinnappa K. Ganapathy , James William Dolter , Vito R. Bica , Jared S. Grubb
发明人： Gregory K. Woods , Chinnappa K. Ganapathy , James William Dolter , Vito R. Bica , Jared S. Grubb
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/00
摘要： An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory.
摘要翻译：一种装置包括第一和第二组件，存储器和分配器，其被配置为将所述存储器的一部分分配给所述第一组件，其中所述第一组件被配置为访问所述存储器的所分配的部分并将信息发送到所述第二组件提供第二组件对存储器的分配部分的访问。

17. 发明授权

US08826093B2 Power saving method for coded transmission 有权
标题翻译：编码传输省电方式
公开(公告)号：US08826093B2
公开(公告)日：2014-09-02
申请号：US11335013
申请日：2006-01-18
申请人： Gordon Kent Walker , Chinnappa K. Ganapathy , Dhinakar Radhakrishnan , Fuyun Ling , Rajiv Vijayan
发明人： Gordon Kent Walker , Chinnappa K. Ganapathy , Dhinakar Radhakrishnan , Fuyun Ling , Rajiv Vijayan
IPC分类号： H04L1/18 , H04L1/00
CPC分类号： H04L1/0053 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L1/0083
摘要： Conserving power for coded transmissions comprises ceasing to process parity packets once associated data packets are deemed correct or corrected. Once data packets are deemed correct or corrected, the receiving unit can shut off during the transmission of parity packets.
摘要翻译：编码传输的节省功率包括：一旦相关联的数据分组被认为是正确的或纠正的，停止处理奇偶分组。一旦数据分组被认为是正确的或纠正的，接收单元可以在传输奇偶分组期间关闭。

18. 发明授权

US08612504B2 IFFT processing in wireless communications 有权
标题翻译：无线通信中的IFFT处理
公开(公告)号：US08612504B2
公开(公告)日：2013-12-17
申请号：US11612456
申请日：2006-12-18
申请人： Jai N. Subrahmanyam , Chinnappa K. Ganapathy , Durk L. Van Veen , Jinxia Bai , Kevin S. Cousineau , Seokyong Oh
发明人： Jai N. Subrahmanyam , Chinnappa K. Ganapathy , Durk L. Van Veen , Jinxia Bai , Kevin S. Cousineau , Seokyong Oh
IPC分类号： G06F17/14 , G06F15/00
CPC分类号： H04L27/2626
摘要： Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.
摘要翻译：描述了执行IFFT流水线技术。在一些方面，流水线通过具有具有第一和第二部分的存储器的处理系统来实现，编码器被配置为处理第一和第二存储器部分中的每一个中的数据;被配置为处理第一和第二部分中的编码数据的IFFT 存储器部分和后处理器，其被配置为在IFFT处理第二存储器部分中的编码数据时处理第一存储器部分中的IFFT处理的数据，后处理器被配置为以与编码器不同的时钟速度操作 IFFT。

19. 发明授权

US08509859B2 Apparatus and methods for control of sleep modes in a transceiver 有权
标题翻译：用于控制收发器中睡眠模式的装置和方法
公开(公告)号：US08509859B2
公开(公告)日：2013-08-13
申请号：US11372876
申请日：2006-03-10
申请人： Tadeusz Jarosinski , Chinnappa K. Ganapathy , Michael Mao Wang
发明人： Tadeusz Jarosinski , Chinnappa K. Ganapathy , Michael Mao Wang
IPC分类号： H04B1/16 , H04B1/38 , H04M1/00
CPC分类号： H04W52/0225 , H04B1/1615 , H04W52/0293 , Y02D70/1222 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.
摘要翻译：公开了用于在收发器或接收器中控制睡眠模式的装置和方法。具体地，公开了一种收发器，其包括被配置为确定关于收发器内的部件的至少一部分的睡眠周期的定时信息的处理器。收发器还包括耦合到处理器的睡眠控制逻辑，以从处理器接收关于睡眠周期的信息，并且被配置为在与处理器无关的功率衰减周期期间实现收发器的至少一部分组件的关闭。

20. 发明授权

US08139612B2 Methods and apparatus for dynamic packet mapping 有权
标题翻译：动态分组映射的方法和装置
公开(公告)号：US08139612B2
公开(公告)日：2012-03-20
申请号：US11398156
申请日：2006-04-04
申请人： Jinxia Bai , Chinnappa K. Ganapathy , Thomas Sun
发明人： Jinxia Bai , Chinnappa K. Ganapathy , Thomas Sun
IPC分类号： H04J13/00 , H04J9/00 , H04J11/00 , H04J1/00
CPC分类号： H04N21/434 , H04L27/2647 , H04L49/9078 , H04W8/26 , H04W28/14
摘要： Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.
摘要翻译：动态分组映射的方法和装置。提供了一种用于映射度量数据以产生与信道相关联的可解码分组的方法。该方法包括获取与度量数据相关联的信道标识符，基于信道标识确定来自多个缓冲器的可用缓冲器，将度量数据写入可用缓冲器，检测何时在多个选定缓冲器中形成可解码分组并且从所选择的缓冲器输出可解码分组。一种装置包括多个缓冲器和映射逻辑，其被配置为获得与度量数据相关联的信道标识符，基于信道标识确定可用缓冲器，将度量数据写入可用缓冲器，检测何时形成可解码分组选择的缓冲器，并从所选缓冲器输出可解码分组。

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