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11. 发明授权

US06951220B1 Method of decontaminating equipment 有权
标题翻译：去污设备的方法
公开(公告)号：US06951220B1
公开(公告)日：2005-10-04
申请号：US10288157
申请日：2002-11-05
申请人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
发明人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
IPC分类号： B08B7/00 , B08B9/00 , C23C16/44
CPC分类号： B08B7/00 , C23C16/4405 , Y10S134/902 , Y10S438/905
摘要： A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperature to cause the wet oxygen or the mixture comprising hydrochloric gas and oxygen to react with the germanium.
摘要翻译：对用于IC制造系统的室进行净化的方法包括在室中提供湿氧气或包含盐酸气体和氧气的混合物，并将室中的温度从第一较低温度升至第二较高温度，以使湿氧气或包含氯化氢气体和氧气的混合物与锗反应。

12. 发明授权

US07001837B2 Semiconductor with tensile strained substrate and method of making the same 有权
标题翻译：具有拉伸应变衬底的半导体及其制造方法
公开(公告)号：US07001837B2
公开(公告)日：2006-02-21
申请号：US10346617
申请日：2003-01-17
申请人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
发明人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
IPC分类号： H01L21/4763
CPC分类号： H01L29/7843 , H01L29/1054 , H01L2924/0002 , Y10S257/90 , Y10S438/933 , H01L2924/00
摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
摘要翻译：示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

13. 发明授权

US07701019B2 Tensile strained substrate 有权
标题翻译：拉伸应变基材
公开(公告)号：US07701019B2
公开(公告)日：2010-04-20
申请号：US11356606
申请日：2006-02-17
申请人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
发明人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7843 , H01L29/1054 , H01L2924/0002 , Y10S257/90 , Y10S438/933 , H01L2924/00
摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
摘要翻译：示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

14. 发明授权

US06867428B1 Strained silicon NMOS having silicon source/drain extensions and method for its fabrication 失效
标题翻译：具有硅源/漏扩展的应变硅NMOS及其制造方法
公开(公告)号：US06867428B1
公开(公告)日：2005-03-15
申请号：US10282712
申请日：2002-10-29
申请人： Paul R. Besser , Eric N. Paton , Qi Xiang
发明人： Paul R. Besser , Eric N. Paton , Qi Xiang
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/6659 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.
摘要翻译： n型应变硅MOSFET利用形成在硅锗衬底上的应变硅沟道区。在应变硅沟道区的相对侧的硅天竺塔层中设置有硅区，并且在硅区域中注入浅的源极和漏极延伸。通过在硅区域而不是在硅锗中形成浅的源极和漏极延伸部分，避免了由锗在锗中增加的扩散速率引起的源极和漏极扩展失真。

15. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

16. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

17. 发明授权

US06811448B1 Pre-cleaning for silicidation in an SMOS process 有权
标题翻译：在SMOS工艺中预硅化硅化
公开(公告)号：US06811448B1
公开(公告)日：2004-11-02
申请号：US10619879
申请日：2003-07-15
申请人： Eric N. Paton , Paul R. Besser , Qi Xiang
发明人： Eric N. Paton , Paul R. Besser , Qi Xiang
IPC分类号： H01L21302
CPC分类号： H01L21/02054 , H01L21/02046 , H01L21/02052 , H01L21/28518 , H01L29/665
摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用用于从晶片顶表面去除自然氧化物的协议。暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。该方案可以使用氟化氢浸渍。在使用等离子体之前可以使用氟化氢浸渍。该协议允许在SMOS器件中更好的硅化。

18. 发明授权

US06764912B1 Passivation of nitride spacer 有权
标题翻译：氮化物间隔物钝化
公开(公告)号：US06764912B1
公开(公告)日：2004-07-20
申请号：US09919943
申请日：2001-08-02
申请人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
发明人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656
摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.
摘要翻译：栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

19. 发明授权

US06602781B1 Metal silicide gate transistors 有权
标题翻译：金属硅化物晶体管
公开(公告)号：US06602781B1
公开(公告)日：2003-08-05
申请号：US09734207
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2144
CPC分类号： H01L21/28202 , H01L21/28097 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/66606 , H01L29/7833
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了金属在凹部中的部分之外，除去金属。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

20. 发明授权

US06465309B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06465309B1
公开(公告)日：2002-10-15
申请号：US09734185
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28097 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.
摘要翻译：半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

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