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11. 发明专利

JP2003141900A NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2003141900A
公开(公告)日：2003-05-16
申请号：JP2001334660
申请日：2001-10-31
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OMURO JITSUWA , OSHIMA KAZUYOSHI , HOSHIDA AKIHIKO , MANITA KIICHI , KANEMITSU MICHITARO , UDO SHINJI , KIKUCHI KAZUE , UJIIE KAZUAKI , SAKAI MASAHIRO
IPC分类号： G11C16/02 , G11C16/34 , G11C29/12 , G11C29/34 , G11C29/44 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To shorten a time required for a test in a nonvolatile semiconductor memory being electrically writable and erasable such as a flash memory. SOLUTION: This device is provided with a counter circuit (50) for counting the number of defects caused by write and erasure of a prescribed unit such as a sector, and a comparing circuit (51) for determining whether a value counted by the counter circuit exceeds an allowable value of the number of defects previously set. When the count value of the counter circuit exceeds the allowable value set to the register, a write operation or an erasure operation is not performed even if a command of write or erasure is inputted from the outside.

12. 发明专利

JPS57177570A JUNCTION TYPE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPS57177570A
公开(公告)日：1982-11-01
申请号：JP6237681
申请日：1981-04-27
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： UJIIE KAZUAKI , YAMAGUCHI KEN
IPC分类号： H01L29/80 , H01L29/10 , H01L29/417
摘要： PURPOSE:To obtain a J-FET with high linear I-V characteristic, by forming two comb gate regions respectively independent on a semiconductor region for a gate being alternately arranged with the intervals therebetween different each other. CONSTITUTION:The n type semiconductor region 2 is epitaxial-grown on an n type Si substrate 1 to diffusion-form the first and second comb p type gate regions 3 and 4 with an SiO2 film with fixed pattern as a mask. At this time, the comb parts 3a-3c and 4a-4c of the regions 3 and 4 are alternately arranged with the intervals different each other. Next, the SiO2 film used for a mask is removed to epitaxial-grow the n type region 2 with small size thereon with the regions 3 and 4 as the burried layers with an n type drain region 5 provided thereon by epitaxial growth to be surrounded by an SiO2 film 6. Thereafter, the film 6 is provided with an opening and a drain electrode 9 contacting the region 5 with the first and second gate electrode 7 and 8 formed on the end parts of the upper surfaces on the regions 3 and 4 and a source electrode 10 on the back of the substrate 1.

13. 发明专利

JPS6124094A Memory device for semiconductor 失效
标题翻译：半导体存储器件
公开(公告)号：JPS6124094A
公开(公告)日：1986-02-01
申请号：JP14238084
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： UJIIE KAZUAKI , SATO NOBUYUKI , TERASAWA MASAAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE: To shorten a rewriting time of data in total by withdrawing a charge inputted by write-in voltage by higher voltage, and by making the length of an erasing time the same degree as that of a write-in time.
CONSTITUTION: A boosting circuit 8 consists of switches MOSFETs Q
1 , Q
2 connected in series with clamp diodes D
1 , D
2 to form a fixed write-in voltage Vpp
1 and an erasing voltage Vpp
2 controlling the voltage generated by charge pump 10 generating far higher voltage than electric source voltage Vcc, pushing up the level gradually receiving supply of charge from electric source voltage Vcc supplied from the outside. The voltage boosted by a charge pump 10 is clamped by break down voltage of clamp diode to generate the stabilized write-in voltage Vpp
1 and erasing voltage Vpp
2 . Thus, the time for rewriting all the data of EEPROM device will be largely shortened.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过以较高的电压撤销由写入电压输入的电荷，并使擦除时间的长度与写入时间相同的程度来缩短数据的重写时间。构成：升压电路8由与钳位二极管D1，D2串联连接的开关MOSFET Q1，Q2组成，以形成固定的写入电压Vpp1，以及擦除电压Vpp2，其控制由电荷泵10产生的电压远高于电压源极电压Vcc，从外部提供的电源电压Vcc向上推动逐渐接收电荷的电平。由电荷泵10升压的电压被钳位二极管的分压钳位，以产生稳定的写入电压Vpp1和擦除电压Vpp2。因此，重写EEPROM设备的所有数据的时间将大大缩短。

14. 发明专利

JPS57177569A JUNCTION TYPE FIELD EFFECT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57177569A
公开(公告)日：1982-11-01
申请号：JP6237581
申请日：1981-04-27
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： UJIIE KAZUAKI , YAMAGUCHI KEN
IPC分类号： H01L29/80 , H01L27/098
摘要： PURPOSE:To allow the on-off action of multisignals and the mixing or resultant of multisignals for the most appropriate state for contactless switches, etc., by providing a plurality of gate and drain regions in a integral body with a source region common. CONSTITUTION:An n type layer 2 is epitaxial-grown on an n type Si substrate 1 serving as a source region with an SiO2 film 3 selectively provided on the center thereof for the diffusion-formation of P type gate regions 4 and 5 with the film as the mask. Next, the film 3 is removed with the epitaxial growth of the n type layer 2 contacting a layer 2 again over the entire surface including the regions 4 and 5 for the diffusion-formation of n type drain regions 6 and 7 corresponded to the regions 4 and 5. Thereafter, the clearance between the regions is filled to adhere an SiO2 film 8 over the entire surface for the formation of the first and second electrodes 9 and 10 which correspond to the regions 4 and 5, and the first and second drain electrodes 11 and 12 are provided corresponding to the regions 6 and 7. Thus, the first transistor 14 is constituted of the regions 4 and 6 and electrodes 9 and 11, and the second transistor 15 of the regions 5 and 7 and electrodes 10 and 12.

15. 发明专利

JPH11144481A SEMICONDUCTOR NON-VOLATILE MEMORY 失效
公开(公告)号：JPH11144481A
公开(公告)日：1999-05-28
申请号：JP31768897
申请日：1997-11-04
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA TOSHIFUMI , YOSHIDA KEIICHI , UJIIE KAZUAKI
IPC分类号： G11C16/02 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To improve flexibility in use while realizing high reliability by externally setting the counting limiting value of the number of times of repetition of the erasing operation in the corresponding unit and erasing determination operation and the number of times of repetition of the write operation and write determination operation on the occasion of setting the erase mode and write mode with externally given command. SOLUTION: A register R1 writes the number of times of write and erase operations for the fixedly preset normal mode through a switch MOSFETQ1 and then transfers it to a counter (A) for monitoring the number of times of write and erase operations. A register 3 transfers the number of times of input write and erase operations to the counter A via a switch MOSFETQ2. A command data determines the normal operation mode or test mode based on the command fetched to the register R2 and the switch MOSFETQ1, Q2 are set to on-condition depending on respective operation mode. Thereby, the testing time can be shortened.

16. 发明专利

JPS60251598A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60251598A
公开(公告)日：1985-12-12
申请号：JP10462984
申请日：1984-05-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , UJIIE KAZUAKI , TERASAWA MASAAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/20 , G11C16/22 , G11C16/30 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent wrong writing and wrong erasure in power-on operation and to eliminate the need for an external additional circuit by stopping substantially the operation of a boosting circuit by using a means which stores one level on the power-on operation. CONSTITUTION:An oscillation circuit OSC outputs pulses phi which vary periodically between a low and a high level when powered on and inverters IV1 and IV2 generate complementary pulses phi and -phi, which are supplied to the boosting circuit VBST. Then, a high voltage VPP of 5VCC is obtained at a capacitor 5 according to the high level of the pulses phi and -phi. The output of an FF as a power-on detecting circuit is held automatically at the high level, then the control signal (c) from a voltage detecting circuit VLD is held at the low level to make the operation of the circuit VBST ineffective, so that the voltage VPP is not outputted any more.

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