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11. 发明专利

JPS63160249A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63160249A
公开(公告)日：1988-07-04
申请号：JP30647386
申请日：1986-12-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIYAMOTO KEIJI , ICHIHARA SEIICHI , MATSUKAWA KEIZO
IPC分类号： H01L21/60
摘要： PURPOSE:To flatten the surface of a bump electrode and to contrive improvement in connecting strength with a lead by a method wherein, in a tape-carrier type device, a bump electrode is formed on the upper part of the external terminal (bonding pad) located in the aperture of the passivation film of a chip. CONSTITUTION:A base metal film 2A and an intermediate conductive film 2B are formed on the surface of the external terminal 1A of a chip 1 and also on the surface of a passivation film 1B. Then, gold is grown on the surface of the film 2B using a plating mask in such a manner that the part smaller in size than the aperture part 1C of the film 1B will be exposed on the flat surface of the film 2B, and a bump electrode 2C is formed. Is the electrode 2C is formed on the flat surface of the external terminal 1A, the surface of the electrode can be made flat, and a recessed part is not generated in the center part of the electrode. Accordingly, the connecting strength with the inner lead can be improved.

12. 发明专利

JPS6381950A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6381950A
公开(公告)日：1988-04-12
申请号：JP22601286
申请日：1986-09-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIYAMOTO KEIJI , ICHIHARA SEIICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To reduce an electric resistance value and a thermal resistance value between a semiconductor chip and a substrate, and to prevent the generation of a crack in a passivation film by interposing a conductive metallic layer scaling down a stepped section formed by an opening to the upper section of a barrier metal layer and shaping a projecting electrode. CONSTITUTION:A conductive metallic layer 5A is formed between a barrier metal layer 4 in an opening 3C section and a projecting electrode 5B. Since the foundation of the projecting electrode 5B can be flattened, the surface (a connecting surface with a lead 6) of the projecting electrode 5B can be flattened. Consequently, the contact area of the projecting electrode 5B and the lead 6 can be increased, thus reducing an electric resistance value and a thermal resistance value. The contact area of the projecting electrode 5B and the lead 6 is augmented, thus lowering pressure applied to a passivation film 3B in a section except the opening 3C section. The pressure drop can prevent the generation of cracks in the passivation film 3B.

13. 发明专利

JPS6379332A FILM CARRIER 失效
公开(公告)号：JPS6379332A
公开(公告)日：1988-04-09
申请号：JP22359386
申请日：1986-09-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIHARA SEIICHI , MIYAMOTO KEIJI , MATSUKAWA KEIZO , YAMADA MUNEHIRO
IPC分类号： H01L21/60 , H01L21/66
摘要： PURPOSE:To obtain a film carrier which is available for testing and which also has antistatic effect, by laminating or spreading an antistatic layer on the peripheral part separated from a pad for testing and the peripheral part of a sprocket. CONSTITUTION:An antistatic layer 6 constituted of conductor foils or carbon tapes in the case of forming a lead is laminated or spread on the peripheral part separated from a pad 5 for testing and the peripheral part of sprocket holes 2. As an antistatic area is formed on the peripheral part of a sprocket holes 2, electrification is reduced, even if a tape is carried by the sprocket holes 2, or a reel and a tape 1 contact with each other. Thereby, a film carrier which is available for test and also has antistatic effect can be obtained.

14. 发明专利

JPS6352431A FILM CARRIER PACKAGE 失效
公开(公告)号：JPS6352431A
公开(公告)日：1988-03-05
申请号：JP19546386
申请日：1986-08-22
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIHARA SEIICHI , WAKASHIMA YOSHIAKI , MIYAMOTO KEIJI
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent a semiconductor element from cracking in a film carrier package in which one side surface is coated or reduced in thickness by cutting by bonding a hard plate on the rear surface of the element. CONSTITUTION:A hard plate 11 is bonded to the rear surface of a chip 7, and composed thinly of, for example, a metal plate or a ceramic plate. The plate 11 is bonded to the rear surface of the chip 7 by an adhesive or an Au-Si eutectic alloy. The warpage of the semiconductor element 7 is reduced due to the contraction of a resin sealing unit 12 to prevent the element 7 from cracking. Even if a microcrack exists by cutting on the rear surface of the chip 7, since the plate 11 is bonded to the rear surface, it can reduce the cracks of the element 1.

15. 发明专利

JPH0427149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SUBSTRATE USED FOR MOUNTING SAME 失效
公开(公告)号：JPH0427149A
公开(公告)日：1992-01-30
申请号：JP13203190
申请日：1990-05-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KAWAKUBO HIROSHI , ICHIHARA SEIICHI , HAGIWARA YASUHISA , KAJIWARA YUJIRO , ONO HIROSHI
IPC分类号： H01L23/50 , H05K3/34
摘要： PURPOSE:To differentiate lengths of leads and to accelerate multiple pins of a surface mounting type LSI package by differentiating outer lead shape of parts of multiple leads extended externally from the side of a package body from the other shape. CONSTITUTION:A semiconductor chip 3 is placed on a tab 4 made of a conductive material, many leads 5 made of the same material as tabs 4 are led from four sides of a package body 2, partial leads 5a and outer lead shape of other leads 5b are pad-led to gull wings in such a manner that the lengths of leads are set to l2, l1 so that the l1 is shorter than the l2. The leads 5a and the leads 5b are alternately disposed along the side of the body 2. Thus, while the profile size of the body remains constant, the number of pins can be increased, the multiple pins of a surface mounting type LSI package can be increased.

16. 发明专利

JPH03291960A SUBSTRATE FOR SEMICONDUCTOR-DEVICE LAMINATION AND LAMINATED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03291960A
公开(公告)日：1991-12-24
申请号：JP9346590
申请日：1990-04-09
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCUMPUTER ENG
发明人： SHIMOISHI TOMOAKI , ICHIHARA SEIICHI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
摘要： PURPOSE:To prevent the dislocation between an interconnection terminal pattern on the surface and an interconnection terminal pattern on the rear when the interconnection terminal patterns are formed on the surface and the rear of an insulating substrate and the interconnection terminal patterns are overlapped by a method wherein identical interconnection terminal patterns are formed on identical faces of one pair of substrates to be overlapped so as to be turned mutually by 180 deg.. CONSTITUTION:These are substrates for semiconductor-device lamination use in which interconnection terminal patterns 9 formed on the surface and the rear of insulating substrates 8 are overlapped and connected electrically. Identical interconnection terminal patterns are formed on identical faces of one pair of substrates for semiconductor-device lamination use to be overlapped in such a way that they are turned mutually by 180 deg.. For example, identical interconnection terminal patterns 9 are formed On identical faces of four identical frame members 8 on an insulating substrate 200 so as to be turned mutually by 180 deg.. That is to say, the identical interconnection terminal patterns 9 as they are and the interconnection terminal patterns 9 which have turned them by 180 deg. are formed alternately. on the identical faces of the individual frame members 8. This assembly is divided and cut off; the identical interconnection terminal patterns 9 formed on the identical faces of the individual frame members 8 are overlapped and connected by using a throguhhole interconnection 10.

17. 发明专利

JPH0341755A MANUFACTURE OF SEMICONDUCTOR DEVICE AND LEAD FRAME 失效
公开(公告)号：JPH0341755A
公开(公告)日：1991-02-22
申请号：JP17735889
申请日：1989-07-10
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KIMOTO RYOSUKE , MATSUZAWA ASAO , KAWAKUBO HIROSHI , ICHIHARA SEIICHI , MOCHIZUKI HIROYUKI , TANAKA HIDEKI , NAKAMURA ATSUSHI
IPC分类号： H01L23/50
摘要： PURPOSE:To prevent the short circuits between neighboring leads by providing a space wherein solder which is crushed and extrudes by clamping can flow in before the solder overflows to the outside of the edges of leads and dams beforehand. CONSTITUTION:In a lead frame 1, recess parts 20 which are recessed one step in the upper and rear surfaces of dams 4 and leads 3 in a region from the approximately central parts of the dams 4 to the intermediate part of an inner lead 7. Spaces 21 are formed. When clamping is performed by a molding die, a part of a device ia positioned at a bottom-force parting surface 29 and a top-force parting surface 30 around a cavity 28 between a bottom force 26 and a top force 27 of the molding die 25 so that said part faces said surfaces 29 and 30 under the close contact state. The edges of the bottom-force parting surface 29 and the top-force parting surface 30 extruding from the sides of the cavity 28 are positioned on the recess parts 20 of a tab 11. As a result, solder which is crushed and flows out in molding flows into the recess parts 20 and does not extend from the edges of leads 3 and the dams 4.

18. 发明专利

JPH02143531A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02143531A
公开(公告)日：1990-06-01
申请号：JP29859988
申请日：1988-11-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： UCHIDA KEN , ITAGAKI TATSUO , SATO TSUNEO , ICHIHARA SEIICHI , NAGASAWA KOICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/321 , H01L21/60
摘要： PURPOSE:To augment the bonding strength of a metallic wiring onto an interlayer insulating film as well as the counter strength of an outer connecting electrode against external force thereby enhancing the reliability of an electrode by a method wherein the bonding strength between the metallic wiring and the underneath interlayer insulating film is augmented by eliminating a barrier layer from an electrode leading out part. CONSTITUTION:A metallic wiring 8 is provided on a PSG 7 while one end of the metallic wiring 8 is connected to a diffused layer 3 via a through hole 7a formed in the PSG film 7 and a CVD film 6. On the other hand, a rectangular electrode leading-out part 9a is formed on the other end of the wiring 8. A final passivation film 9 is formed on the metallic wiring 8 while the electrode leading-out part 8a is externally exposed from another through hole 8a made in the passivation film 9. In such a constitution, the metallic wiring 8 is composed of an Al-Si alloy while a barrier layer 12 is partially laid down underneath the metallic wiring 8. That is, the barrier layer 12 is provided on the contact part of the said N diffused layer 3 and the peripheral part thereof but not provided underneath the electrode leading-out part 8a.

19. 发明专利

JPH01191452A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01191452A
公开(公告)日：1989-08-01
申请号：JP1445088
申请日：1988-01-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ICHIHARA SEIICHI , MATSUKAWA KEIZO , KOYAMA HIROSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent the occurrence of defects such as cracks in the periphery of each electrode of a pellet and to improve the reliability of a semiconductor device, by bonding an inner lead to a bump wherein at least a part of the inner lead has a porous state. CONSTITUTION:A porous bump 4a is obtained as follows: a bump 4 comprising gold is formed on the surface of a barrier metal layer 10b by a plating method; gold paste is deposited on the upper part of the bump 4 by a screen printing method and the like; and the bump is heated at about 100 deg.C. The following steps are performed when an inner lead 6a is bonded to the porous bump 4a: the gold or tin plated inner lead 6a is overlapped on the porous bump 4a; a bonding tool 11 is heated to about 50 deg.C; and the bonding tool 11 is pushed to the lead from the upper part so as to apply a load. Sintering reaction of gold grains constituting the porous bump 4a is made to progress by the heat of the tool 11. Thus, the bonding of the inner lead 6a and the porous bump 4a is achieved. At this time, the soft porous bump 4a is deformed, and stress is absorbed.

20. 发明专利

JPS6379348A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6379348A
公开(公告)日：1988-04-09
申请号：JP22359986
申请日：1986-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIYAMOTO KEIJI , ICHIHARA SEIICHI , MATSUKAWA KEIZO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
摘要： PURPOSE:To alleviate stress, which is applied to an external electrode at the time of bonding by an organic film and to enhance reliability, by providing the organic film between the peripheral part of the external electrode and an insulating film comprising an inorganic film in a ring shape. CONSTITUTION:An organic film 10 is formed in a ring shaped pattern so that the central part of an aluminum layer 9, which is a part of a bump electrode 2, is exposed. The organic film 10 is provided only at the periphery of the bump electrode 2 on a semiconductor chip 1. The film is not provided at a part other than said periphery. Therefore, an insulating film 8, which is an inorganic film, is exposed at the part other than the periphery of the bump electrode 2. Since the organic film 10 is provided only at the peripheral part of the bump electrode 2, stress due to thermal expansion with respect to a packaging material 15 is less and the film 10 is hard to be separated. Since depositing property between the packaging material and the insulating film 8 is excellent, the insulating film 8 is not separated due to the difference in thermal expansions with respect to the packaging material 15.

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