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11. 发明专利

HK588A SEMICONDUCTOR MEMORY DEVICE 未知
公开(公告)号：HK588A
公开(公告)日：1988-01-15
申请号：HK588
申请日：1988-01-07
申请人： HITACHI LTD
发明人： MATSUMOTO TETSURO , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/418 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/408 , G11C11/413 , G11C8/00
摘要： A semiconductor memory device has three address decoder circuits that select word lines. Since the word lines are selected by the three address decoder circuits, it is allowed to reduce the number of unit decoder circuits that constitute the address decoder circuits. Therefore, the load for the address buffer circuit can be reduced, and operation can be carried out at high speeds. Further, the decrease in the number of unit decoder circuits results in the decrease in the consumption of electric power.

12. 发明专利

DE3432973A1 未知
公开(公告)号：DE3432973A1
公开(公告)日：1985-03-28
申请号：DE3432973
申请日：1984-09-07
申请人： HITACHI LTD
发明人： MATSUMOTO TETSURO , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/418 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/408 , G11C11/413 , G11C8/02
摘要： A semiconductor memory device has three address decoder circuits that select word lines. Since the word lines are selected by the three address decoder circuits, it is allowed to reduce the number of unit decoder circuits that constitute the address decoder circuits. Therefore, the load for the address buffer circuit can be reduced, and operation can be carried out at high speeds. Further, the decrease in the number of unit decoder circuits results in the decrease in the consumption of electric power.

13. 发明专利

IT8424228D0 未知
公开(公告)号：IT8424228D0
公开(公告)日：1984-12-21
申请号：IT2422884
申请日：1984-12-21
申请人： HITACHI LTD
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C5/06 , G11C11/401 , G11C8/00 , G11C8/14 , G11C8/18 , G11C11/407 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , G11C
摘要： Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

14. 发明专利

IT8422604D0 未知
公开(公告)号：IT8422604D0
公开(公告)日：1984-09-11
申请号：IT2260484
申请日：1984-09-11
申请人： HITACHI LTD
发明人： MATSUMOTO TETSURO , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/418 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/408 , G11C11/413 , G11C
摘要： A semiconductor memory device has three address decoder circuits that select word lines. Since the word lines are selected by the three address decoder circuits, it is allowed to reduce the number of unit decoder circuits that constitute the address decoder circuits. Therefore, the load for the address buffer circuit can be reduced, and operation can be carried out at high speeds. Further, the decrease in the number of unit decoder circuits results in the decrease in the consumption of electric power.

15. 发明专利

DE69718129T2 未知
公开(公告)号：DE69718129T2
公开(公告)日：2003-10-23
申请号：DE69718129
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G05B9/03 , G06F11/00 , G06F11/16 , G06F11/18

16. 发明专利

SG68634A1 Dynamic memory 未知
公开(公告)号：SG68634A1
公开(公告)日：1999-11-16
申请号：SG1997003540
申请日：1997-09-24
申请人： HITACHI ULSI ENG CORP , HITACHI LTD
发明人： NAKAMURA MASAYUKI , HASEGAWA MASATOSHI , NARUI SEIJI , TANAKA YOUSUKE , MIYATAKE SHINICHI , KUBOUCHI SHUICHI , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C11/34
摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

17. 发明专利

SG54456A1 Semconductor integrated circuit device and method for manufacturing the same 未知
公开(公告)号：SG54456A1
公开(公告)日：1998-11-16
申请号：SG1997000019
申请日：1997-01-07
申请人： HITACHI LTD
发明人： NARUI SIEJI , UDAGAWA TETSU , TAKAKURA IRUMA-SHI , KAJIGAYA KAZUHIKO , YOSHIDA MAKOTO
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/04 , H01L21/44
摘要： The sheet resistance of a gate electrode 8 A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL 1 , BL 2 are, respectively, 2 Omega/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8 A (the word line WL) or the bit lines BL 1 , BL 2 by which the number of the steps of manufacturing the DRAM can be reduced.

18. 发明专利

HK47990A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：HK47990A
公开(公告)日：1990-06-29
申请号：HK47990
申请日：1990-06-21
申请人： HITACHI LTD
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C5/06 , G11C8/00 , G11C8/14 , G11C11/401 , G11C8/18 , G11C11/407 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , G11C5/02 , H03M7/22
摘要： Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

19. 发明专利

GB2152752B SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2152752B
公开(公告)日：1988-03-02
申请号：GB8431412
申请日：1984-12-12
申请人： HITACHI LTD
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C5/06 , G11C8/00 , G11C11/401 , G11C8/14 , G11C8/18 , G11C11/407 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , G11C5/02
摘要： Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

20. 发明专利

GB2152752A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2152752A
公开(公告)日：1985-08-07
申请号：GB8431412
申请日：1984-12-12
申请人： HITACHI LTD
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C5/06 , G11C8/00 , G11C11/401 , G11C8/14 , G11C8/18 , G11C11/407 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , G11C5/02
摘要： Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

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