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11. 发明申请

US20060179237A1 Method and apparatus for performing data prefetch in a multiprocessor system 失效
标题翻译：在多处理器系统中执行数据预取的方法和装置
公开(公告)号：US20060179237A1
公开(公告)日：2006-08-10
申请号：US11054173
申请日：2005-02-09
申请人： James Fields , Benjiman Goodman , Guy Guthrie , Jeffrey Stuecheli
发明人： James Fields , Benjiman Goodman , Guy Guthrie , Jeffrey Stuecheli
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0831 , G06F12/0851
摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.
摘要翻译：公开了一种用于在多处理器系统中执行数据预取的方法和装置。多处理器系统包括多个处理器，每个具有高速缓冲存储器。缓存存储器被细分成多个片段。一组预取请求最初由多处理器系统中的请求处理器发出。每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

12. 发明申请

US20060179183A1 Single burst completion of multiple writes at buffered DIMMs 审中-公开
标题翻译：在缓冲DIMM上单次完成多次写入
公开(公告)号：US20060179183A1
公开(公告)日：2006-08-10
申请号：US11054372
申请日：2005-02-09
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/161 , G11C5/04
摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.
摘要翻译：在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。因此，针对同一DIMM的多个写入被缓存。当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

13. 发明申请

US20080077744A1 Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request 失效
标题翻译：通过延长响应Snoop请求的时间减少被拒绝的侦听请求数
公开(公告)号：US20080077744A1
公开(公告)日：2008-03-27
申请号：US11950717
申请日：2007-12-05
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

14. 发明申请

US20070266126A1 DATA PROCESSING SYSTEM AND METHOD OF DATA PROCESSING SUPPORTING TICKET-BASED OPERATION TRACKING 审中-公开
标题翻译：数据处理系统和数据处理方法支持基于票单的操作跟踪
公开(公告)号：US20070266126A1
公开(公告)日：2007-11-15
申请号：US11279643
申请日：2006-04-13
申请人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/173
CPC分类号： G06F12/0831 , G06F12/0897 , G06F12/1458
摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.
摘要翻译：数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送处理单位。该通信包括具有请求的操作和表示对请求的系统响应的组合响应。至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

15. 发明申请

US20060179337A1 Data processing system, method and interconnect fabric for synchronized communication in a data processing system 失效
标题翻译：数据处理系统，方法和互连结构，用于数据处理系统中的同步通信
公开(公告)号：US20060179337A1
公开(公告)日：2006-08-10
申请号：US11055299
申请日：2005-02-10
申请人： Benjiman Goodman , Guy Guthrie , Praveen Reddy , William Starke , Jeffrey Stuecheli
发明人： Benjiman Goodman , Guy Guthrie , Praveen Reddy , William Starke , Jeffrey Stuecheli
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.
摘要翻译：数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

16. 发明申请

US20060179272A1 Data processing system, method and interconnect fabric for partial response accumulation in a data processing system 失效
标题翻译：数据处理系统，数据处理系统部分响应累积的方法和互连结构
公开(公告)号：US20060179272A1
公开(公告)日：2006-08-10
申请号：US11055297
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/00
CPC分类号： G06F13/385 , G06F9/546
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个处理单位。互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应响应。

17. 发明申请

US20060179254A1 Data processing system, method and interconnect fabric supporting destination data tagging 有权
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US20060179254A1
公开(公告)日：2006-08-10
申请号：US11055405
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

18. 发明申请

US20080028155A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COHERENCY COMMUNICATION UTILIZING COHERENCY DOMAIN INDICATORS 有权
标题翻译：数据处理系统和方法，用于有效的通信使用相关域指标
公开(公告)号：US20080028155A1
公开(公告)日：2008-01-31
申请号：US11835259
申请日：2007-08-07
申请人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

19. 发明申请

US20070277026A1 PROCESSOR, METHOD, AND DATA PROCESSING SYSTEM EMPLOYING A VARIABLE STORE GATHER WINDOW 有权
标题翻译：处理器，方法和数据处理系统使用可变存储GATHER窗口
公开(公告)号：US20070277026A1
公开(公告)日：2007-11-29
申请号：US11836872
申请日：2007-08-10
申请人： ROBERT BELL , Hugh Shen , Jeffrey Stuecheli , Derek Williams
发明人： ROBERT BELL , Hugh Shen , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F9/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

20. 发明申请

US20070239939A1 Apparatus for Performing Stream Prefetch within a Multiprocessor System 审中-公开
标题翻译：用于在多处理器系统中执行流预取的装置
公开(公告)号：US20070239939A1
公开(公告)日：2007-10-11
申请号：US11278825
申请日：2006-04-06
申请人： Benjiman Goodman , Jeffrey Stuecheli
发明人： Benjiman Goodman , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： An apparatus for performing stream prefetch within a multiprocessor system is disclosed. The multiprocessor system includes a first and second processors, and each of the processors includes a primary cache and a secondary cache. A stream register having multiple entries is initially provided within the first processor, and at least one of the entries in the stream register includes a prefetch history field. The bit in the prefetch history field associated with a sequential address stream is set in response to the sequential address stream being found in the secondary cache of the second processor after a system memory operation has been performed by the first processor. The bit in the prefetch history field associated with the same sequential address stream is reset in response to the sequential address stream not being found in the secondary cache of the second processor after a cache memory operation has been performed by the first processor. The bit in the prefetch history field serves as a basis for a subsequent prefetch on the same sequential address stream to decide whether the data should come from a cache memory operation or a system memory operation.
摘要翻译：公开了一种用于在多处理器系统内执行流预取的装置。多处理器系统包括第一和第二处理器，并且每个处理器包括主缓存和次级高速缓存。最初在第一处理器内提供具有多个条目的流寄存器，并且流寄存器中的条目中的至少一个包括预取历史字段。响应于在由第一处理器执行系统存储器操作之后在第二处理器的辅助高速缓存中找到顺序地址流，设置与顺序地址流相关联的预取历史字段中的位。响应于在由第一处理器执行高速缓存存储器操作之后在第二处理器的二次高速缓存中未找到顺序地址流，复位与相同顺序地址流相关联的预取历史字段中的位。预取历史字段中的位用作相同序列地址流上的后续预取的基础，以决定数据是来自高速缓冲存储器操作还是系统存储器操作。

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