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    • 11. 发明授权
    • Field-effect-controllable semiconductor component
    • 场效应可控半导体元件
    • US5923066A
    • 1999-07-13
    • US940473
    • 1997-09-30
    • Jenoe Tihanyi
    • Jenoe Tihanyi
    • H01L29/10H01L29/739H01L29/78H01L29/87
    • H01L29/1095H01L29/7391H01L29/7397
    • A field-effect-controllable semiconductor component includes a semiconductor body with first and second surfaces. An inner zone of a first conduction type adjoins the first surface. An anode zone of the opposite, second conduction type adjoins the inner zone in the direction of the first surface and adjoins the second surface in the opposite direction. At least one first base zone of the second conduction type is embedded in the first surface. At least one source zone of the first conduction type is embedded in the first surface. At least one source electrode makes contact with the base zones and the source zones. At least one gate electrode is insulated from the semiconductor body and the source electrode by a gate oxide and at least partly covers parts of the first base zones appearing at the first surface. Intermediate cell zones contain the source zones. Trenches enclose the intermediate cell zones and are insulated from the intermediate cell zones by a gate oxide. Gate electrode pins in the trenches are connected to the gate electrode running on the first surface.
    • 场效应可控半导体部件包括具有第一和第二表面的半导体本体。 第一导电类型的内部区域与第一表面相邻。 相对的第二导电类型的阳极区域在第一表面的方向上与内部区域相邻,并且在相反方向上与第二表面相邻。 第二导电类型的至少一个第一基区被嵌入在第一表面中。 第一导电类型的至少一个源极区被嵌入在第一表面中。 至少一个源极与基极区和源极区接触。 至少一个栅电极通过栅极氧化物与半导体本体和源电极绝缘,并且至少部分地覆盖出现在第一表面处的第一基区的部分。 中间单元区域包含源区域。 沟槽包围中间细胞区域,并通过栅极氧化物与中间细胞区域绝缘。 沟槽中的栅电极引脚连接到在第一表面上运行的栅电极。
    • 13. 发明授权
    • Circuit configuration for detecting a load current of a power
semiconductor component with a source-side load
    • 用于检测源极侧负载的功率半导体部件的负载电流的电路结构
    • US5815027A
    • 1998-09-29
    • US660500
    • 1996-06-07
    • Jenoe TihanyiAdam-Istvan Koroncai
    • Jenoe TihanyiAdam-Istvan Koroncai
    • G01R1/20G01R19/00G05F1/10G05F3/24G01R19/165
    • G05F3/24G01R1/203G01R19/0092H03K17/145H03K2217/0027
    • A field-effect-controllable power semiconductor component has a drain terminal, a source terminal, a gate terminal, a drain-to-source voltage and a load current. A circuit configuration for detecting the load current of the power semiconductor component includes a further field-effect-controllable semiconductor component through which a fraction of the load current flows. The further semiconductor component has a drain terminal connected to the drain terminal of the power semiconductor component, a gate terminal connected to the gate terminal of the power semiconductor component, a source terminal and a drain-to-source voltage. A resistor at which a voltage proportional to the load current can be picked up, is connected to a fixed potential terminal. A controllable resistor is connected between the resistor and the source terminal of the further semiconductor component. The controllable resistor adjusts the current of the further semiconductor component so that the drain-to-source voltages of the power semiconductor component and the further semiconductor component are equal to one another.
    • 场效应可控功率半导体元件具有漏极端子,源极端子,栅极端子,漏极 - 源极电压和负载电流。 用于检测功率半导体部件的负载电流的电路结构包括另外的场效应可控半导体部件,一部分负载电流通过该半导体部件流动。 另外的半导体部件具有连接到功率半导体部件的漏极端子的漏极端子,连接到功率半导体部件的栅极端子的栅极端子,源极端子和漏极到源极电压。 可以拾取与负载电流成比例的电压的电阻器连接到固定电位端子。 可控电阻器连接在电阻器和另一半导体部件的源极端子之间。 可控电阻调节另外的半导体元件的电流,使得功率半导体元件和另外的半导体元件的漏 - 源电压彼此相等。
    • 16. 发明授权
    • Integrated comparator circuit
    • 集成比较电路
    • US5434521A
    • 1995-07-18
    • US978637
    • 1992-11-19
    • Ludwig LeipoldRainald SanderJenoe Tihanyi
    • Ludwig LeipoldRainald SanderJenoe Tihanyi
    • G01R19/165H03K5/08H03K17/30H03K17/687H03K5/153
    • H03K17/6872G01R19/16519H03K17/302
    • An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.
    • 集成比较器电路包括两个互补MOSFET,其中主电流路径在连接点处串联在一起连接在一起。 反相器级具有两个互补MOSFET,栅极端子连接到连接点。 首先,提供第二和第三终端。 第一和第二端子用于工作电压,第二和第三端子用于比较电压。 串联电路连接在第一和第三端子之间,变频器级连接在第一和第二端子之间。 连接到第一端子的串联电路的MOSFET之一和连接到第一端子的反相器级的MOSFET之一具有相同的通道类型。 连接到第三端子的串联电路的另一个MOSFET和连接到第二端子的反相器级的另一个MOSFET具有相同的通道类型。
    • 18. 发明授权
    • Circuit limiting the load current of a power MOSFET
    • 电路限制功率MOSFET的负载电流
    • US5272399A
    • 1993-12-21
    • US4970
    • 1993-01-15
    • Jenoe TihanyiLudwig LeipoldRainald Sander
    • Jenoe TihanyiLudwig LeipoldRainald Sander
    • H02H7/20H03K17/08H03K17/082H03K3/01H03K5/08
    • H03K17/0822
    • A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.
    • 用于限制流过功率MOSFET的电流的电路配置包括分压器,其连接在功率MOSFET的漏极和源极端子之间,并且具有在功率MOSFET的漏极 - 源极电压之后的电压下降的节点。 控制晶体管具有连接在功率MOSFET的栅极端子和源极端子之间的负载路径。 如果功率MOSFET的漏极 - 源极电压超过预定值,则控制晶体管作为分压器节点处的电压的函数导通。 电阻连接在控制晶体管的栅极端子和功率MOSFET的栅极端子之间。 耗尽FET具有连接到控制晶体管的栅极端子的漏极端子。 耗尽FET的源极端子连接到分压器的节点。 耗尽FET的栅极端子连接到功率MOSFET的源极端子。