专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5859797A Biasing circuit for UPROM cells with low voltage supply 失效
标题翻译：低压电源的UPROM单元的偏置电路
公开(公告)号：US5859797A
公开(公告)日：1999-01-12
申请号：US846753
申请日：1997-04-30
申请人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
发明人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
IPC分类号： G11C16/30 , G11C7/00
CPC分类号： G11C16/30
摘要： A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
摘要翻译：一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。

12. 发明授权

US07602225B2 Power on reset circuit for a digital device including an on-chip voltage down converter 有权
标题翻译：包括片内降压转换器的数字设备的上电复位电路
公开(公告)号：US07602225B2
公开(公告)日：2009-10-13
申请号：US11829413
申请日：2007-07-27
申请人： Donghyun Seo , Jacopo Mulatti , Taegyoung Kang
发明人： Donghyun Seo , Jacopo Mulatti , Taegyoung Kang
IPC分类号： H03K3/02
CPC分类号： H03K17/223 , G06F1/24 , G06F1/28
摘要： A power on reset circuit initializes at power on a digital integrated circuit, and includes a first power on reset signal generator powered by an external power supply voltage and generates a first power on reset signal. A reference voltage generator is powered by the external power supply voltage, and is enabled by the first power on reset signal for generating a stable compensating reference voltage. A voltage down converter circuit receives the reference voltage and is enabled by the first power on reset signal, and converts the external applied power supply voltage to a stable regulated internal supply voltage. A second power on reset signal generator circuit receives the regulated internal supply voltage, and is enabled by the first power on reset signal for generating a second power on reset signal for core parts of the digital integrated circuit for initializing them at power on.
摘要翻译：上电复位电路在数字集成电路通电时初始化，并且包括由外部电源电压供电的第一上电复位信号发生器，并产生第一上电复位信号。参考电压发生器由外部电源电压供电，并通过第一个上电复位信号使能，以产生稳定的补偿参考电压。降压转换器电路接收参考电压并通过第一上电复位信号使能，并将外部施加的电源电压转换为稳定的稳压内部电源电压。第二上电复位信号发生器电路接收稳压的内部电源电压，并且由第一上电复位信号使能以产生用于数字集成电路的核心部分的第二上电复位信号，以便在通电时进行初始化。

13. 发明授权

US07558152B2 Address counter for nonvolatile memory device 有权
标题翻译：非易失性存储器地址计数器
公开(公告)号：US07558152B2
公开(公告)日：2009-07-07
申请号：US11829527
申请日：2007-07-27
申请人： Hyungsang Lee , Dae Sik Song , Jacopo Mulatti
发明人： Hyungsang Lee , Dae Sik Song , Jacopo Mulatti
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C16/08
摘要： An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.
摘要翻译：用于非易失性存储器件的地址计数器包括级联的单元。每个单元包括地址计数触发器，其被更新为每个新计数的地址位的值，或者在ALE周期期间锁存由存储器件的外部用户输入的列地址位值，以寻址所选择的开始存储器位置页。每个单元还包括附加地址加载触发器，用于在ALE周期期间加载列地址位值输入，以在ALE周期期间寻址所选页面上的起始存储器位置。逻辑电路在读取序列中的读取确认周期期间和在程序序列的第一个数据输入周期期间将地址计数触发器更新为地址位值。

14. 发明授权

US07385850B2 Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory 有权
标题翻译：非易失性存储器和相对NAND闪速存储器的单元的编程和验证方法
公开(公告)号：US07385850B2
公开(公告)日：2008-06-10
申请号：US11539708
申请日：2006-10-09
申请人： Kuhong Jeong , Hyungsang Lee , Jacopo Mulatti
发明人： Kuhong Jeong , Hyungsang Lee , Jacopo Mulatti
IPC分类号： G11C11/34 , G11C7/10
CPC分类号： G11C16/3459 , G11C16/3454 , G11C29/832 , G11C2216/14
摘要： A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory are verified that they have been correctly copied into corresponding cells of the destination page. The method carries out the fast but inadequate-at-times Global Verify operation, and if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation is carried out, which is slower but accurate.
摘要翻译：在非易失性存储器中编程单元的方法是基于全局验证操作和逐字节验证操作。非易失性存储器的目的地页面的单元被编程，并且存储在相同存储器的源页面的编程单元中的逻辑值被证实已被正确复制到目的地页面的相应单元中。该方法执行快速但不足的全局验证操作，并且如果全局验证操作在一定次数的尝试中失败，则会执行逐字节验证操作，这是较慢但准确的。

15. 发明申请

US20080049542A1 ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器地址计数器
公开(公告)号：US20080049542A1
公开(公告)日：2008-02-28
申请号：US11829580
申请日：2007-07-27
申请人： Hyungsang Lee , Dae Sik Song , Jacopo Mulatti
发明人： Hyungsang Lee , Dae Sik Song , Jacopo Mulatti
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C16/08
摘要： An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.
摘要翻译：用于非易失性存储器件的地址计数器包括级联的单元。每个单元包括地址计数触发器，其被更新为每个新计数的地址位的值，或者在ALE周期期间锁存由存储器件的外部用户输入的列地址位值，以寻址所选择的开始存储器位置页。每个单元还包括附加地址加载触发器，用于在ALE周期期间加载列地址位值输入，以在ALE周期期间寻址所选页面上的起始存储器位置。逻辑电路在读取序列中的读取确认周期期间和在程序序列的第一个数据输入周期期间将地址计数触发器更新为地址位值。

16. 发明申请

US20070109866A1 METHOD OF PROGRAMMING AND VERIFYING CELLS OF A NONVOLATILE MEMORY AND RELATIVE NAND FLASH MEMORY 有权
标题翻译：非易失性存储器和相关NAND闪存存储器的编程和验证方法
公开(公告)号：US20070109866A1
公开(公告)日：2007-05-17
申请号：US11539708
申请日：2006-10-09
申请人： Kuhong Jeong , Hyungsang Lee , Jacopo Mulatti
发明人： Kuhong Jeong , Hyungsang Lee , Jacopo Mulatti
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C16/3454 , G11C29/832 , G11C2216/14
摘要： A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory are verified that they have been correctly copied into corresponding cells of the destination page. The method carries out the fast but inadequate-at-times Global Verify operation, and if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation is carried out, which is slower but accurate.
摘要翻译：在非易失性存储器中编程单元的方法是基于全局验证操作和逐字节验证操作。非易失性存储器的目的地页面的单元被编程，并且存储在相同存储器的源页面的编程单元中的逻辑值被证实已被正确复制到目的地页面的相应单元中。该方法执行快速但不足的全局验证操作，并且如果全局验证操作在一定次数的尝试中失败，则会执行逐字节验证操作，这是较慢但准确的。

17. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

18. 发明授权

US6101118A Voltage regulator for single feed voltage memory circuits, and flash type memory in particular 有权
标题翻译：单馈电压存储电路的电压调节器，特别是闪存型存储器
公开(公告)号：US6101118A
公开(公告)日：2000-08-08
申请号：US196204
申请日：1998-11-20
申请人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
发明人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
IPC分类号： G11C5/14 , G11C16/30 , G11C11/24
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.
摘要翻译：用于存储器电路的电压调节器具有差分级，其具有接收与温度无关的控制电压的非反相输入端; 连接到接地电压基准的反相输入端子; 连接到适于产生升压电压的升压电路的馈电端子; 以及连接到所述电压调节器的输出端子的输出端子，用于从输入电压的比较开始产生输出电压基准。电压调节器还包括插入差分级的馈电端子和输出端子之间的连接晶体管，连接晶体管是源极跟随器，其具有连接到差分级的输出端子的控制端子，以及连接到电压调节器的输出端子，以自限制输出端子上的电压的转换。

19. 发明授权

US06016073A BiCMOS negative charge pump 失效
标题翻译： BiCMOS负电荷泵
公开(公告)号：US06016073A
公开(公告)日：2000-01-18
申请号：US965068
申请日：1997-11-05
申请人： Andrea Ghilardelli , Jacopo Mulatti , Maurizio Branchetti
发明人： Andrea Ghilardelli , Jacopo Mulatti , Maurizio Branchetti
IPC分类号： H01L21/8247 , H01L21/8234 , H01L27/088 , H01L29/788 , H01L29/792 , H02M3/07 , G06F1/10
CPC分类号： H02M3/073
摘要： A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.
摘要翻译：电荷泵包括串联连接在电荷泵的参考电位和输出端之间的多个级。多个级包括靠近参考电位的第一组级，以及靠近电荷泵输出端的第二组级。第一组的每个级包括通过晶体管，其中第一和第二端子分别连接到级的输入端和输出端，第一电容器具有连接到级的输出端的第一板和由第一板驱动的第二板数字信号在参考电压和正电压之间切换。第二组的每一级包括结二极管，其具有连接到该级的输入的第一电极和连接到该级的输出的第二电极，以及一第二电容器，该第二电容器具有连接到该级的输出的第一电极和第二板由参考电压和电压源之间的数字信号切换驱动。

20. 发明申请

US20080028182A1 ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20080028182A1
公开(公告)日：2008-01-31
申请号：US11829527
申请日：2007-07-27
申请人： Hyungsang LEE , Dae Sik SONG , Jacopo Mulatti
发明人： Hyungsang LEE , Dae Sik SONG , Jacopo Mulatti
IPC分类号： G06F12/06
CPC分类号： G11C8/04 , G11C16/08
摘要： An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式