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11. 发明授权

US5943571A Method for manufacturing fine structures 失效
标题翻译：制造精细结构的方法
公开(公告)号：US5943571A
公开(公告)日：1999-08-24
申请号：US883571
申请日：1997-06-26
申请人： Herbert Schaefer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
发明人： Herbert Schaefer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
IPC分类号： C23C16/04 , H01L21/033 , H01L21/20 , H01L21/205 , H01L21/266 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , C23C16/04 , H01L21/02381 , H01L21/02425 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/0334 , H01L27/11517 , H01L29/66825
摘要： For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.
摘要翻译：为了制造精细结构，使用在载气中使用含有SiH 4和GeH 4的第一工艺气体时，在CVD工艺的基板的表面上形成限定精细结构的尺寸的核。核可以同时用作掩模，例如蚀刻或注入时，以及保留在结构中的有源或无源部件，例如作为电荷存储在EEPROM的电介质中。

12. 发明授权

US06552385B2 DRAM memory capacitor having three-layer dielectric, and method for its production 有权
标题翻译：具有三层电介质的DRAM存储电容器及其制造方法
公开(公告)号：US06552385B2
公开(公告)日：2003-04-22
申请号：US09756082
申请日：2001-01-08
申请人： Gerhard Beitel , Martin Franosch , Thomas Peter Haneder , Gerrit Lange , Hans Reisinger , Herbert Schäfer , Stephan Schlamminger , Hermann Wendt
发明人： Gerhard Beitel , Martin Franosch , Thomas Peter Haneder , Gerrit Lange , Hans Reisinger , Herbert Schäfer , Stephan Schlamminger , Hermann Wendt
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/02197 , H01L21/02266 , H01L21/31691
摘要： A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.
摘要翻译：描述了包含BaSrTiO 3（BST）电介质的DRAM电容器。该电介质具有能够形成电子槽的三层结构，其中电子可以永久性地被捕获。

13. 发明授权

US06867105B2 Bipolar transistor and method of fabricating a bipolar transistor 有权
标题翻译：双极晶体管和制造双极晶体管的方法
公开(公告)号：US06867105B2
公开(公告)日：2005-03-15
申请号：US10215152
申请日：2002-08-08
申请人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
发明人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.
摘要翻译：双极晶体管包括具有集电极的第一层。第二层具有用于基座的基部切口。第三层包括用于底座的引线。第三层形成有用于发射极的发射极切口。在与基座切口相邻的第二层中形成底切。基部至少部分位于底切中。为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。中间层相对于第二层可选择性地蚀刻。至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。在与基底的接触区域中去除中间层。

14. 发明授权

US06197666B1 Method for the fabrication of a doped silicon layer 有权
标题翻译：掺杂硅层的制造方法
公开(公告)号：US06197666B1
公开(公告)日：2001-03-06
申请号：US09390496
申请日：1999-09-03
申请人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Hans Reisinger , Matthias Ilg
发明人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Hans Reisinger , Matthias Ilg
IPC分类号： H01L2120
CPC分类号： H01L27/10873 , C23C16/24 , C23C16/56 , H01L21/28035 , H01L21/32055 , H01L21/76877
摘要： A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.
摘要翻译：一种用于制造掺杂硅层的方法，包括通过使用含有SiH 4，Si 2 H 6和掺杂气体的工艺气体进行沉积。由此制造的掺杂硅层既可以用作MOS晶体管的栅电极，也可以用作导电连接。在50至200nm的厚度之间，其电阻率小于或等于0.5mOMEGAcm。

15. 发明授权

US07612430B2 Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar transistor 有权
标题翻译：硅双极晶体管，电路布置和制造硅双极晶体管的方法
公开(公告)号：US07612430B2
公开(公告)日：2009-11-03
申请号：US10297421
申请日：2001-06-15
申请人： Martin Franosch , Thomas Meister , Herbert Schäfer , Reinhard Stengl , Konrad Wolf
发明人： Martin Franosch , Thomas Meister , Herbert Schäfer , Reinhard Stengl , Konrad Wolf
IPC分类号： H01L29/732
CPC分类号： H01L29/1004
摘要： The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).
摘要翻译：硅双极晶体管（100）包括具有一起形成基极的第一高掺杂基极层（105）和第二较差掺杂的基极层（106）的基极。发射极是完全高度掺杂的，直接安装在第二基极层（106）上。

16. 发明授权

US5817553A Process for manufacturing capacitors in a solid state configuration 失效
标题翻译：用于制造固态配置的电容器的工艺
公开(公告)号：US5817553A
公开(公告)日：1998-10-06
申请号：US766977
申请日：1996-12-16
申请人： Reinhard Stengl , Martin Franosch , Hermann Wendt
发明人： Reinhard Stengl , Martin Franosch , Hermann Wendt
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.
摘要翻译：制造用于动态存储单元配置的电容器，特别是用于动态存储单元配置的层叠电容器，是通过首先形成一层层而制成的，该层包括由与第二材料制成的层交替的第一导电材料制成的层。可以相对于第一材料选择性地蚀刻第二材料。层状结构由层序列形成，层状结构的侧面各自具有导电支撑结构。层状结构形成有诸如间隙的开口，其中层的表面暴露在其中。由第二材料制成的层相对于由第一材料制成的层选择性地去除。由第一材料和支撑结构制成的层的暴露表面设置有电容器电介质，其上放置有相对电极。电容器是通过蚀刻对p +掺杂多晶硅有选择性的p掺杂多晶硅制成的。

17. 发明授权

US07135757B2 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US07135757B2
公开(公告)日：2006-11-14
申请号：US10912344
申请日：2004-08-04
申请人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
发明人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.
摘要翻译：双极晶体管包括具有集电极的第一层。第二层具有用于基座的基部切口。第三层包括用于底座的引线。第三层形成有用于发射极的发射极切口。在与基座切口相邻的第二层中形成底切。基部至少部分位于底切中。为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。中间层相对于第二层可选择性地蚀刻。至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。在与基底的接触区域中去除中间层。

18. 发明授权

US06635545B2 Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor 失效
公开(公告)号：US06635545B2
公开(公告)日：2003-10-21
申请号：US10160630
申请日：2002-06-03
申请人： Josef Böck , Wolfgang Klein , Herbert Schäfer , Martin Franosch , Thomas Meister , Reinhard Stengl
发明人： Josef Böck , Wolfgang Klein , Herbert Schäfer , Martin Franosch , Thomas Meister , Reinhard Stengl
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

19. 发明申请

US20050006723A1 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US20050006723A1
公开(公告)日：2005-01-13
申请号：US10912344
申请日：2004-08-04
申请人： Reinhard Stengl , Thomas Meister , Herbert Schafer , Martin Franosch
发明人： Reinhard Stengl , Thomas Meister , Herbert Schafer , Martin Franosch
IPC分类号： H01L21/331 , H01L29/732 , H01L31/0328
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.
摘要翻译：双极晶体管包括具有集电极的第一层。第二层具有用于基座的基部切口。第三层包括用于底座的引线。第三层形成有用于发射极的发射极切口。在与基座切口相邻的第二层中形成底切。基部至少部分位于底切中。为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。中间层相对于第二层可选择性地蚀刻。至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。在与基底的接触区域中去除中间层。

20. 发明授权

US07064360B2 Bipolar transistor and method for fabricating it 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07064360B2
公开(公告)日：2006-06-20
申请号：US10470816
申请日：2002-02-04
申请人： Martin Franosch , Thomas Meister , Herbert Schaefer , Reinhard Stengl
发明人： Martin Franosch , Thomas Meister , Herbert Schaefer , Reinhard Stengl
IPC分类号： H01L31/0328
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.
摘要翻译：提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。此外，很大程度上避免了与点缺陷相关的困难。

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