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11. 发明申请

US20110138249A1 Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code 审中-公开
标题翻译：用于检测由纠错码编码的多个编码二进制字中的错误的装置和方法
公开(公告)号：US20110138249A1
公开(公告)日：2011-06-09
申请号：US12959817
申请日：2010-12-03
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/13 , G01L9/0052 , G01L9/0073 , G01L9/0098 , G01L13/025 , G01L15/00 , H03M13/1515 , H03M13/152 , H03M13/155 , H03M13/19 , H03M13/3746
摘要： An apparatus for detecting an error within a plurality of coded binary words coded by an error correction code includes a combiner connected town error detector. The combiner generates a combined binary word by combining a first coded binary word and a second coded binary word of the plurality of coded binary words, so that the determined combined binary word is a code word of the error correction code if the first coded binary word and the second coded binary word are code words of the error correction code, and so that the combined binary word is not a code word of the error correction code if the first coded binary word or the second coded binary word is not a code word of the error correction code. Further, the error detector may determine an error detection bit sequence indicating whether or not the combined binary word is a code word of the error correction code.
摘要翻译：用于检测由纠错码编码的多个编码二进制字中的错误的装置包括组合器连接的城镇错误检测器。组合器通过组合多个编码二进制字中的第一编码二进制字和第二编码二进制字来产生组合二进制字，使得所确定的组合二进制字是纠错码的码字，如果第一编码二进制字并且第二编码二进制字是纠错码的码字，并且如果第一编码二进制字或第二编码二进制字不是码字，则组合二进制字不是纠错码的码字纠错码。此外，误差检测器可以确定指示组合二进制字是否是纠错码的码字的错误检测比特序列。

12. 发明申请

US20070168814A1 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US20070168814A1
公开(公告)日：2007-07-19
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

13. 发明申请

US20060284637A1 Circuit for compression and storage of circuit diagnosis data 有权
标题翻译：用于压缩和存储电路诊断数据的电路
公开(公告)号：US20060284637A1
公开(公告)日：2006-12-21
申请号：US11367715
申请日：2006-03-06
申请人： Frank Poehl , Jan Rzeha , Matthias Beck , Michael Goessel , Peter Muhmenthaler
发明人： Frank Poehl , Jan Rzeha , Matthias Beck , Michael Goessel , Peter Muhmenthaler
IPC分类号： G01R31/26
CPC分类号： G01R31/318335 , G01R31/31813
摘要： A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.
摘要翻译：压实机包括可连接到电路的电路输出，测试比较输入和测试数据输出的测试数据输入。压实机还包括多个H矩阵XOR门，其被布置为在测试数据输入和测试数据输出之间的切换机构，使得施加到测试数据输入的数据在根据H的系数压缩的测试数据输出处产生纠错码的矩阵，以及布置在测试数据输入和测试数据输出之间的补偿XOR门，每个补偿XOR门包括用于接收补偿值的输入。

14. 发明授权

US08898529B2 High performance compaction for test responses with many unknowns 有权
标题翻译：具有许多未知数的测试响应的高性能压实
公开(公告)号：US08898529B2
公开(公告)日：2014-11-25
申请号：US13643107
申请日：2011-05-18
申请人： Michael Goessel , Michael Richter , Thomas Rabenalt
发明人： Michael Goessel , Michael Richter , Thomas Rabenalt
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318563 , G01R31/318583
摘要： A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m
摘要翻译：一种电路装置，用于利用具有N个扫描路径的电子电路的X值来控制对测试和诊断数据的掩蔽，其中测试数据在由具有m个输入和N个输出的解压缩器插入到N个扫描路径中时提供（m

15. 发明授权

US08312332B2 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US08312332B2
公开(公告)日：2012-11-13
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

16. 发明授权

US08136009B2 Circuit arrangement and method for error detection and arrangement for monitoring of a digital circuit 有权
标题翻译：用于数字电路监控的错误检测和布置的电路布置和方法
公开(公告)号：US08136009B2
公开(公告)日：2012-03-13
申请号：US12188746
申请日：2008-08-08
申请人： Michael Goessel , Egor Sogomonyan
发明人： Michael Goessel , Egor Sogomonyan
IPC分类号： G06F11/00
CPC分类号： H03M13/00
摘要： A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E1, . . . , En for inputting n (n≧2) information bits x1, . . . , xn and m binary outputs for outputting m (m≧1) check bits c1, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi1, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi1, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x1, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f1(x11, . . . , x1n1) of the form c1=f1(x11, . . . , x1n1)=f11(x11, x12) XOR f12(x13, x14) XOR . . . XOR f1k1(x1(n1−1), x1n1) at a first output for outputting a first check bit c1, wherein n1 is an even number where n1≧2 and 2 k1=n1 and the Boolean functions f11(x11, x12), . . . , f1k1(x1(n1−1), x1n1) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c11, . . . , c1k1.
摘要翻译：电路装置如下形成。组合电路具有n个二进制输入E1。。。，En用于输入n（n≥2）个信息位x1。。。，xn和m个二进制输出，用于输出m（m≥1）个校验位c1，。。。，厘米。组合电路被配置为实现i = 1的布尔函数ci = fi（xi1，...，xini）。。。，m在第i个输出端用于确定校验位ci，其中集合{xi1，...，。。，xini}在确定校验位ci的ni信息位是所有n个信息位{x1，...的子集。。。，xn}。组合电路还被配置为实现形式为c1 = f1（x11，...，x1n1）= f11（x11，x12）XOR f12（x13，x14）的第一布尔函数f1（x11，...，x1n1））异或。。。用于输出第一校验位c1的第一输出处的XOR f1k1（x1（n1-1），x1n1），其中n1是其中n1≥2和2k1 = n1的偶数，以及布尔函数f11（x11，x12）。。。在每种情况下，f1k1（x1（n1-1），x1n1））可以由具有两个输入和一个输出的逻辑门实现的两个变量的非线性布尔函数，其中逻辑门各自具有控制值c11。。。，c1k1。

17. 发明授权

US07979783B2 Error detection device and method for error detection for a command decoder 有权
标题翻译：用于命令解码器的错误检测装置和错误检测方法
公开(公告)号：US07979783B2
公开(公告)日：2011-07-12
申请号：US11672652
申请日：2007-02-08
申请人： Michael Goessel , Franz Klug , Steffen Marc Sonnekalb
发明人： Michael Goessel , Franz Klug , Steffen Marc Sonnekalb
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/10
摘要： An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein the sequence of control signal words has at least one control signal word, having: a controller designed to provide the input word at a first time and the input word at a second time for reading out the command memory, wherein the second time is delayed with respect to the first time, to effect a readout of the sequence of control signal words at a first time and a readout of the sequence of control signal words at a second time; and a comparator designed to receive and compare the associated sequences of control signal words read out at the first and second times, and to output a signal indicating an error if the associated sequences of control signal words read out at the first and second times are different.
摘要翻译：描述了一种用于命令解码器的错误检测装置，命令解码器基于输入字从命令存储器中读出相关序列的控制信号字，其中控制信号字序列具有至少一个控制信号字，具有：控制器，其被设计为在第一时间提供输入字，并且输入字在第二时间用于读出指令存储器，其中第二时间相对于第一次被延迟，以实现控制信号序列的读出第一时间的字和读出控制信号字的序列; 以及比较器，用于接收和比较在第一次和第二次读出的控制信号字的相关序列，并且如果在第一次和第二次读出的相关序列的控制信号字不同，则输出指示错误的信号。

18. 发明申请

US20090049369A1 Circuit Arrangement and Method for Error Detection and Arrangement for Monitoring of a Digital Circuit 有权
标题翻译：电路布置及数字电路监控误差检测与布置方法
公开(公告)号：US20090049369A1
公开(公告)日：2009-02-19
申请号：US12188746
申请日：2008-08-08
申请人： Michael Goessel , Egor Sogomonyan
发明人： Michael Goessel , Egor Sogomonyan
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/00
摘要： A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E1, . . . , En for inputting n (n≧2) information bits x1, . . . , xn and m binary outputs for outputting m (m≧1) check bits c1, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi1, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi1, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x1, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f1(x11, . . . , x1n1) of the form c1=f1(x11, . . . , x1n1)=f11(x11, x12) XOR f12(x13, x14) XOR . . . XOR f1k1(x1(n1−1), x1n1) at a first output for outputting a first check bit c1, wherein n1 is an even number where n1≧2 and 2 k1=n1 and the Boolean functions f11(x11, x12), . . . , f1k1(x1(n1−1), x1n1) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c11, . . . , c1k1.
摘要翻译：电路装置如下形成。组合电路具有n个二进制输入E1。。。，En用于输入n（n> = 2）个信息位x1。。。，xn和m个二进制输出，用于输出m（m> = 1）校验位c1，。。。，厘米。组合电路被配置为实现i = 1的布尔函数ci = fi（xi1，...，xini）。。。，m在第i个输出端用于确定校验位ci，其中集合{xi1，...，。。，xini}在确定校验位ci的ni信息位是所有n个信息位{x1，...的子集。。。，xn}。组合电路还被配置为实现形式为c1 = f1（x11，...，x1n1）= f11（x11，x12）XOR f12（x13，x14）的第一布尔函数f1（x11，...，x1n1））异或。。。用于输出第一校验位c1的第一输出处的XOR f1k1（x1（n1-1），x1n1），其中n1是其中n1> = 2和2k1 = n1的偶数，并且布尔函数f11（x11，x12），。。。在每种情况下，f1k1（x1（n1-1），x1n1））可以由具有两个输入和一个输出的逻辑门实现的两个变量的非线性布尔函数，其中逻辑门各自具有控制值c11。。。，c1k1。

19. 发明申请

US20080263421A1 Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit 有权
标题翻译：电气诊断电路和集成电路测试和/或诊断分析方法
公开(公告)号：US20080263421A1
公开(公告)日：2008-10-23
申请号：US10568842
申请日：2004-08-11
申请人： Michael Goessel , Andreas Leininger
发明人： Michael Goessel , Andreas Leininger
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
摘要翻译：公开了电诊断电路和测试方法。在一个实施例中，用于测试集成电路的电诊断电路包括多个外部输入，多个基本相似的串联连接的开关单元和电路输出。开关单元被构造为可控制的，使得根据开关单元的控制信号存在于开关单元的内部输入端的输入信号可以被不变地转发到开关单元的内部输入端在每种情况下布置在下游，或者可以在外部输入处存在的每种情况下与测试信号组合。

20. 发明授权

US09118351B2 System and method for signature-based redundancy comparison 有权
标题翻译：用于基于签名的冗余比较的系统和方法
公开(公告)号：US09118351B2
公开(公告)日：2015-08-25
申请号：US13430126
申请日：2012-03-26
申请人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
发明人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
IPC分类号： G06F11/00 , H03M13/37 , G05B19/042 , G05B9/03 , G06F11/16 , G06F11/10 , G06F11/14 , H03M13/03 , H03M13/15 , H03M13/19 , H03M13/25 , H03M13/29 , H03M13/00
CPC分类号： H03M13/3746 , G05B9/03 , G05B19/0428 , G06F11/00 , G06F11/1048 , G06F11/1479 , G06F11/1641 , H03M13/033 , H03M13/155 , H03M13/19 , H03M13/258 , H03M13/2948 , H03M13/2957 , H03M13/2966 , H03M13/299 , H03M13/37 , H03M13/3738 , H03M13/3784 , H03M13/6575
摘要： A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
摘要翻译：一种用于基于签名的冗余比较的系统和方法，用于由主机部分接收输入信号，并由主机部分产生二进制输出信号，基于输入信号产生延迟的输入信号，产生第一输出基于所述二进制输出信号的签名，以及基于所述第一输出签名生成延迟的第一输出签名。该系统和方法还包括基于延迟的输入信号产生延迟的二进制输出信号，由检验器部分基于延迟的二进制输出信号产生延迟的第二输出签名，将延迟的第一输出签名与延迟的第二输出进行比较签名并产生误差信号，其中误差信号的状态基于比较。

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