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11. 发明申请

US20120150473A1 CLOCK EDGE GROUPING FOR AT-SPEED TEST 失效
标题翻译：时钟边缘分组用于速度测试
公开(公告)号：US20120150473A1
公开(公告)日：2012-06-14
申请号：US12967885
申请日：2010-12-14
申请人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
IPC分类号： G06F19/00
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.
摘要翻译：一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

12. 发明授权

US07685542B2 Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing 失效
标题翻译：用于在高速测试期间关闭跨异步时钟域的数据捕获的方法和装置
公开(公告)号：US07685542B2
公开(公告)日：2010-03-23
申请号：US11672973
申请日：2007-02-09
申请人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
IPC分类号： G06F17/50 , G01R31/28 , G01R31/02 , G06F11/00
CPC分类号： G01R31/318594
摘要： A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.
摘要翻译：一种用于测试跨异步时钟域配置的逻辑设备的方法包括：在高速故障测试期间，对于具有至少一个数据输入的第一多个锁存器中的每个锁存器，在源于位于异步时钟域内的源的情况下停用本地时钟信号对此。多个锁存器中的每个锁存器的本地时钟信号的去激活以允许在第一多个锁存器内进行数据捕获的方式来实现，并且其中多个锁存器中的每一个的本地时钟信号的去激活进一步以在速度测试期间允许从其到下游闩锁的高速数据发射的方式实现。

13. 发明授权

US07779375B2 Design structure for shutting off data capture across asynchronous clock domains during at-speed testing 失效
标题翻译：用于在高速测试期间关闭跨异步时钟域的数据捕获的设计结构
公开(公告)号：US07779375B2
公开(公告)日：2010-08-17
申请号：US11873543
申请日：2007-10-17
申请人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
IPC分类号： G06F17/50 , G06F11/00 , H04L1/18 , G01R31/28
CPC分类号： G01R31/318583 , G01R31/318594
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于测试跨异步时钟域配置的逻辑设备的设备，包括用于在高速故障测试期间停用第一多个锁存器具有至少一个数据输入，源自位于相对于其的异步时钟域内的源; 其中所述去激活机构被配置为允许在所述第一多个锁存器内的数据捕获，并且其中所述停用机构进一步被配置为允许在速度测试期间从所述第一多个锁存器到其下游锁存器的高速数据发射。

14. 发明申请

US20090102507A1 DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING 失效
标题翻译：用于在速度测试期间切断异步时钟域的数据捕获的设计结构
公开(公告)号：US20090102507A1
公开(公告)日：2009-04-23
申请号：US11873543
申请日：2007-10-17
申请人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
IPC分类号： H03K19/00
CPC分类号： G01R31/318583 , G01R31/318594
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于测试跨异步时钟域配置的逻辑设备的设备，包括用于在高速故障测试期间停用第一多个锁存器具有至少一个数据输入，源自位于相对于其的异步时钟域内的源; 其中所述去激活机构被配置为允许在所述第一多个锁存器内的数据捕获，并且其中所述停用机构进一步被配置为允许在速度测试期间从所述第一多个锁存器到其下游锁存器的高速数据发射。

15. 发明申请

US20080195905A1 METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING 失效
标题翻译：用于在速度测试期间切断异步时钟域的数据捕获的方法和装置
公开(公告)号：US20080195905A1
公开(公告)日：2008-08-14
申请号：US11672973
申请日：2007-02-09
申请人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
IPC分类号： G06F11/25
CPC分类号： G01R31/318594
摘要： A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.
摘要翻译：一种用于测试跨异步时钟域配置的逻辑设备的方法包括：在高速故障测试期间，对于具有至少一个数据输入的第一多个锁存器中的每个锁存器，在源于位于异步时钟域内的源的情况下停用本地时钟信号对此。多个锁存器中的每个锁存器的本地时钟信号的去激活以允许在第一多个锁存器内进行数据捕获的方式来实现，并且其中多个锁存器中的每一个的本地时钟信号的去激活进一步以在速度测试期间允许从其到下游闩锁的高速数据发射的方式实现。

16. 发明授权

US07793176B2 Method of increasing path coverage in transition test generation 失效
标题翻译：在过渡测试生成中增加路径覆盖的方法
公开(公告)号：US07793176B2
公开(公告)日：2010-09-07
申请号：US11696981
申请日：2007-04-05
申请人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
发明人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31707 , G01R31/318328
摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.
摘要翻译：一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。随着每个电路路径的测试，沿着电路路径的测试电路节点被标记为“行使”。随后的测试路径通过避免标记的电路节点进行组装。以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

17. 发明授权

US07784000B2 Identifying sequential functional paths for IC testing methods and system 有权
标题翻译：识别IC测试方法和系统的顺序功能路径
公开(公告)号：US07784000B2
公开(公告)日：2010-08-24
申请号：US12050381
申请日：2008-03-18
申请人： Gary D. Grise , Vikram Iyengar
发明人： Gary D. Grise , Vikram Iyengar
IPC分类号： G06F17/50
CPC分类号： G01R31/318594 , G01R31/31858
摘要： A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.
摘要翻译：公开了一种识别IC测试方法的顺序功能路径的方法和系统。在一个实施例中，方法可以包括用于高速结构测试的顺序功能路径识别的方法，所述方法包括：使用定时工具来枚举电路中的多个关键路径; 识别多个关键路径中的哪一个是在IC的功能操作期间将起作用的顺序功能路径，其通过识别多个关键路径中的哪一个可以产生用于使用具有n个功能捕获周期的测试序列的测试，其中n更大比2; 使用启动扫描测试序列对顺序功能路径执行路径测试生成; 并对使用不具有扫描测试序列测试的关键路径进行路径测试，使用具有两个功能捕获的启动捕获测试序列。

18. 发明申请

US20080250279A1 Method of Increasing Path Coverage in Transition Test Generation 失效
标题翻译：在过渡测试生成中增加路径覆盖的方法
公开(公告)号：US20080250279A1
公开(公告)日：2008-10-09
申请号：US11696981
申请日：2007-04-05
申请人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
发明人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31707 , G01R31/318328
摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.
摘要翻译：一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。随着每个电路路径的测试，沿电路路径的测试电路节点被标记为“行使”。通过避免标记的电路节点组装后续测试路径。以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

19. 发明申请

US20090240459A1 INDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND SYSTEM 有权
标题翻译：识别IC测试方法和系统的顺序功能模块
公开(公告)号：US20090240459A1
公开(公告)日：2009-09-24
申请号：US12050381
申请日：2008-03-18
申请人： Gary D. Grise , Vikram Iyengar
发明人： Gary D. Grise , Vikram Iyengar
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/31858
摘要： A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.
摘要翻译：公开了一种识别IC测试方法的顺序功能路径的方法和系统。在一个实施例中，方法可以包括用于高速结构测试的顺序功能路径识别的方法，所述方法包括：使用定时工具来枚举电路中的多个关键路径; 识别多个关键路径中的哪一个是在IC的功能操作期间将起作用的顺序功能路径，通过识别多个关键路径中的哪一个可以产生用于使用具有n个功能捕获周期的测试序列的测试，其中n更大比2; 使用启动扫描测试序列对顺序功能路径执行路径测试生成; 并对使用不具有扫描测试序列测试的关键路径进行路径测试，使用具有两个功能捕获的启动捕获测试序列。

20. 发明授权

US08423847B2 Microcontroller for logic built-in self test (LBIST) 有权
公开(公告)号：US08423847B2
公开(公告)日：2013-04-16
申请号：US13469604
申请日：2012-05-11
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

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