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11. 发明授权

US06472624B1 In-line flow switch 失效
标题翻译：在线流量开关
公开(公告)号：US06472624B1
公开(公告)日：2002-10-29
申请号：US09669661
申请日：2000-09-26
申请人： Jaime Harris , Gary Brown , Joel Fisher
发明人： Jaime Harris , Gary Brown , Joel Fisher
IPC分类号： H01H3540
CPC分类号： H01H35/405 , H01H9/08 , H03K17/97
摘要： A flow switch for a high pressure washing system or other flow-related system is disclosed. The flow switch switches from an open to a closed position in the presence of adequate flow in a water or other fluid-carrying pipe. The flow switch includes a cartridge body, a sensor, a plunger, a magnet, and a spring. The cartridge body has an inlet port and an outlet port which allows fluid to flow into the cartridge body, through a flow chamber, and out of the cartridge body. The cartridge body also has a sensor chamber for accommodating the sensor. The sensor is positioned within the sensor chamber and is used to determine whether fluid is flowing through the flow chamber. A plunger is positioned within the flow chamber, and is responsive to fluid flow. Between the plunger and the sensor is a spring. The spring prevents the plunger from coming in close proximity to the sensor absent fluid flow. However, when there is fluid flow, the spring is compressed and the plunger comes in close proximity to the sensor and communicates with the sensor to allow the sensor to determine that fluid is flowing through the flow chamber. The flow switch can also include a housing, which accommodates the cartridge, sensor, plunger, and spring.
摘要翻译：公开了一种用于高压清洗系统或其它流量相关系统的流量开关。在水或其他流体输送管道中存在足够的流动的情况下，流量开关从打开位置切换到关闭位置。流量开关包括盒体，传感器，柱塞，磁体和弹簧。药筒本体具有入口和出口，其允许流体通过流动室流入药筒本体并从药筒本体流出。盒体还具有用于容纳传感器的传感器室。传感器位于传感器室内，用于确定流体是否流经流动室。柱塞位于流动室内，并且响应于流体流动。柱塞和传感器之间是弹簧。弹簧防止柱塞靠近传感器进入，没有流体流动。然而，当存在流体流动时，弹簧被压缩并且柱塞紧邻传感器并与传感器连通以允许传感器确定流体流过流动室。流动开关还可以包括容纳盒，传感器，柱塞和弹簧的壳体。

12. 发明授权

US06394241B1 Energy absorbing shear strip bender 有权
标题翻译：吸能剪板机
公开(公告)号：US06394241B1
公开(公告)日：2002-05-28
申请号：US09421413
申请日：1999-10-21
申请人： Stanley Desjardins , Gary Brown
发明人： Stanley Desjardins , Gary Brown
IPC分类号： F16F712
CPC分类号： F16F7/12
摘要： A simple, low cost energy absorbing shear strip bender that provides constant load, tailored load, or adjustable load/displacement profiles for use in any application where a single use energy absorber is required. Examples include, but are not limited to: a spinal load attenuator for use in crash-resistant aircraft seats; crash-resistant aircraft landing gear; aircraft or automotive restraint harness attachments; cargo or high-mass item tie-downs; automotive bumper attachments; and collapsible steering columns. The present invention comprises a shear plate or other base material, a shear strip integral to the shear plate, and a shear strip tab, all of which are formed from a single sheet of ductile material. The energy absorber attaches to two objects and begins to displace when opposing forces applied to the shear plate and shear strip tab reach the design limit value such that shear strip shears and plastically deforms, i.e., bends. The load that must be applied to stroke the energy absorber is the sum of the shearing force and the bending force. The direction of motion is generally parallel to the shearing plate, but may deviate from parallel by as much as 90°.
摘要翻译：一种简单，低成本的能量吸收剪切带弯曲机，其提供恒定载荷，定制负载或可调载荷/位移曲线，用于需要单次使用能量吸收器的任何应用中。示例包括但不限于：用于防撞飞机座椅的脊柱负载衰减器; 防撞飞机起落架; 飞机或汽车约束线束附件; 货物或大宗物品捆绑; 汽车保险杠附件; 和可折叠转向柱。本发明包括剪切板或其他基材，与剪切板一体的剪切条和剪切条形突片，所有这些都由单片延性材料形成。能量吸收器连接到两个物体，并且当施加到剪切板和剪切条形突片上的相反的力达到设计极限值时开始移位，使得剪切带剪切并塑性变形，即弯曲。施加能量吸收器所需的载荷是剪切力和弯曲力之和。运动方向大致平行于剪切板，但可能会平行偏离多达90°。

13. 发明授权

US5864228A Current mirror current source with current shunting circuit 失效
标题翻译：具有电流分流电路的电流镜电流源
公开(公告)号：US5864228A
公开(公告)日：1999-01-26
申请号：US831368
申请日：1997-04-01
申请人： Gary Brown , John Andrew Campbell , Jitendra Mohan
发明人： Gary Brown , John Andrew Campbell , Jitendra Mohan
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/262
摘要： A stacked current mirror circuit includes four N-channel MOS transistors. One transistor serves as an input device for conducting via its drain, a majority of the reference current. Another transistor is connected as a mirroring device, with its drain coupled to a voltage source, its gate coupled to the gate of the input device, and its source coupled to the source of the input device at a first common node. These two transistors couple to form a first current mirror circuit which couples to the input of a second current mirror comprising the third and fourth transistors. The drain and gate of the third transistor couple to the first common node and the gate of the fourth transistor. The sources of both the third and fourth transistors couple to a second common node (e.g., ground), and the drain of the fourth transistor provides the output. As a result, current is mirrored from the input device transistor to the mirroring device transistor, and then forced through the third transistor. The current is then mirrored from the third transistor to the fourth transistor which forces the current to the output line.
摘要翻译：叠层电流镜电路包括四个N沟道MOS晶体管。一个晶体管用作通过其漏极导通的输入装置，大部分参考电流。另一个晶体管被连接成镜像装置，其漏极耦合到电压源，其栅极耦合到输入装置的栅极，其源极在第一公共节点耦合到输入装置的源极。这两个晶体管耦合以形成第一电流镜电路，其耦合到包括第三和第四晶体管的第二电流镜的输入。第三晶体管的漏极和栅极耦合到第一公共节点和第四晶体管的栅极。第三和第四晶体管的源极耦合到第二公共节点（例如，接地），并且第四晶体管的漏极提供输出。结果，电流从输入器件晶体管镜像到镜像器件晶体管，然后被强制通过第三晶体管。电流然后从第三晶体管镜像到强制电流到输出线的第四晶体管。

14. 发明申请

US20120004619A1 NEEDLE PROTECTIVE DEVICE 审中-公开
标题翻译：针式保护装置
公开(公告)号：US20120004619A1
公开(公告)日：2012-01-05
申请号：US13077625
申请日：2011-03-31
申请人： JOHN D. STEPHENS , John Muri , Ken Garry , Ron Bark , John Detloff , James O'Conner , Gary Brown
发明人： JOHN D. STEPHENS , John Muri , Ken Garry , Ron Bark , John Detloff , James O'Conner , Gary Brown
IPC分类号： A61M5/32
CPC分类号： A61M5/158 , A61M5/3257 , A61M2005/1581
摘要： A needle protective device is provided for reducing inadvertent needle sticks. The needle protective device includes a tubular member that is attached to a base cap. A spring and a shield are positioned in the base cap to selectively cover an access hole of the chamber so that after use of the needle, a needle tip and blood-borne pathogens on the needle are encased within the base cap. The device is selectively pre-activated and is configured such that when activated, the needle tip is contained in the base cap and the device becomes un-usable.
摘要翻译：提供针保护装置以减少无意的针刺。针保护装置包括附接到基盖的管状构件。弹簧和护罩定位在基座盖中以选择性地覆盖腔室的进入孔，使得在使用针之后，针头上的针尖和血源性病原体被包围在基座内。该装置被选择性地预激活并且被配置为使得当被激活时，针尖被包含在基座盖中，并且该装置变得不可用。

15. 发明申请

US20060218381A1 Rounding correction for add-shift-round instruction with dual-use source operand for DSP 审中-公开
标题翻译：用于DSP的双用途操作数的加法移位循环指令的舍入校正
公开(公告)号：US20060218381A1
公开(公告)日：2006-09-28
申请号：US11090440
申请日：2005-03-24
申请人： Chad Fogg , Darrell Boggs , Christopher Jones , Gary Brown
发明人： Chad Fogg , Darrell Boggs , Christopher Jones , Gary Brown
IPC分类号： G06F9/44
CPC分类号： G06F7/49947 , G06F5/01 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167
摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an encoded immediate which specifies the shift count N. The processor corrects after the addition and shifting for an absent rounding bias added 2N-1. The ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2) >>N
摘要翻译：一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。源操作数可以直接指定操作数值或控制值，另一个被隐式指定。或者，可以从源操作数值隐式指定和派生两者。操作数值和控制值中的至少一个是隐式的，未指定。执行加法和右移和舍入的ADDSRN指令，其中源操作数之一是指定移位计数N的编码立即数。处理器在加法和移位之后校正不加舍入偏差，加上2×N 1 。 ADDSRN指令用于加速数字信号处理代码序列，格式为：=（A + B + C + D ... + M + 2）>> N

16. 发明申请

US20060218380A1 Add-shift-round instruction with dual-use source operand for DSP 审中-公开
标题翻译：用于DSP的双用源操作数的移位循环指令
公开(公告)号：US20060218380A1
公开(公告)日：2006-09-28
申请号：US11090441
申请日：2005-03-24
申请人： Darrell Boggs , Chad Fogg , Christopher Jones , Gary Brown
发明人： Darrell Boggs , Chad Fogg , Christopher Jones , Gary Brown
IPC分类号： G06F9/30
CPC分类号： G06F9/30163 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3885
摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an immediate which specifies the shift count N and the processor derives a third added 2N−1, and the ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2N−1)>>N
摘要翻译：一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。源操作数可以直接指定操作数值或控制值，另一个被隐式指定。或者，可以从源操作数值隐式指定和派生两者。操作数值和控制值中的至少一个是隐式的，未指定。 ADDSRN指令执行相加和右移和舍入，其中一个源操作数是指定移位计数N的立即数，并且处理器导出第三个添加的2 N-1，并且ADDSRN 指令用于加速数字信号处理代码序列，格式为<？in-line-formula description =“In-line Formulas”end =“lead”？> dest：=（A + B + C + D ... + M + 2 N-1）>> N <？in-line-formula description =“In-line Formulas”end =“tail”？>

17. 发明申请

US20060095714A1 Clip instruction for processor 审中-公开
标题翻译：处理器的剪辑指令
公开(公告)号：US20060095714A1
公开(公告)日：2006-05-04
申请号：US10982662
申请日：2004-11-03
申请人： Darrell Boggs , Christopher Jones , Gary Brown
发明人： Darrell Boggs , Christopher Jones , Gary Brown
IPC分类号： G06F15/00
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30036
摘要： A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector.
摘要翻译：处理器ISA指令，其执行强制数据元素在指定范围内的限幅操作。 SIMD处理器ISA指令，其对源操作数向量中的每个数据元素执行限幅操作。

18. 发明申请

US20060095713A1 Clip-and-pack instruction for processor 审中-公开
标题翻译：处理器的Clip-and-pack指令
公开(公告)号：US20060095713A1
公开(公告)日：2006-05-04
申请号：US10982268
申请日：2004-11-03
申请人： Darrell Boggs , Christopher Jones , Gary Brown
发明人： Darrell Boggs , Christopher Jones , Gary Brown
IPC分类号： G06F15/00
CPC分类号： G06F9/3001 , G06F9/30021 , G06F9/30036
摘要： A processor ISA instruction which performs a clipping operation forcing a data element to be within a specified range. A SIMD processor ISA instruction which performs a clipping operation upon each data element in a source operand vector. A SIMD processor ISA instruction which performs clipping upon each data elements in each of a plurality of source operand vectors, and performs picking, rounding, and packing upon the clipped operand vectors to generate a single result vector.
摘要翻译：处理器ISA指令，其执行强制数据元素在指定范围内的限幅操作。 SIMD处理器ISA指令，其对源操作数向量中的每个数据元素执行限幅操作。 SIMD处理器ISA指令，对多个源操作数向量中的每一个中的每个数据元素执行限制，并且在剪切的操作数向量上执行拾取，舍入和打包以生成单个结果向量。

19. 发明申请

US20060036801A1 Scalable matrix register file 审中-公开
标题翻译：可扩展矩阵寄存器文件
公开(公告)号：US20060036801A1
公开(公告)日：2006-02-16
申请号：US10916747
申请日：2004-08-11
申请人： Christpher Jones , Gary Brown , Darrell Boggs
发明人： Christpher Jones , Gary Brown , Darrell Boggs
IPC分类号： G06F12/00
CPC分类号： G06F12/0207
摘要： A register file in which the physical row/column mapping is decoupled from the logical row/column mapping. The physical register file includes R*C N-bit storage elements arranged in R rows and C columns. Each physical row includes an N-bit bus, a log2(C)-bit storage element selection line, and a log2(C)-bit output column selection line. In either a logical row or logical column access, no more than one storage element is selected per physical row and coupled to that row's bus, and each column's vertical bit line is uniquely coupled to one row's bus. The values on the storage element selection lines and on the output column selection lines determines which storage elements are coupled to which vertical bit lines. The width C of the register file, the number of rows R of the register file, and the size N of the fundamental data storage element can be independently changed without affecting the others. The size X of the X*N-bit logical data elements can be changed without changing R, C, N, or the width of the buses. The same addressing logic is used, regardless of data size and regardless of whether the access is logically row-wise or column-wise. Horizontal wire count is minimized by an appropriate logical-to-physical mapping of the storage cells.
摘要翻译：物理行/列映射与逻辑行/列映射分离的寄存器文件。物理寄存器文件包括以R行和C列排列的R * C N位存储元件。每个物理行包括N位总线，对数（2）（C）位存储元件选择行和对数2（C）位输出列选择行。在逻辑行或逻辑列访问中，每个物理行选择不超过一个存储元素并耦合到该行的总线，并且每列的垂直位线唯一地耦合到一行总线。存储元件选择线和输出列选择线上的值确定哪些存储元件被耦合到哪个垂直位线。寄存器文件的宽度C，寄存器文件的行数R和基本数据存储元件的大小N可以独立地改变而不影响其他。可以在不改变R，C，N或总线宽度的情况下改变X * N位逻辑数据元素的大小X. 使用相同的寻址逻辑，无论数据大小如何，无论访问是逻辑上是逐行还是逐列。通过存储单元的适当的逻辑到物理映射最小化水平线数。

20. 发明授权

US06636102B1 Polyfuse trim read cell 有权
标题翻译： Polyfuse修剪读取单元格
公开(公告)号：US06636102B1
公开(公告)日：2003-10-21
申请号：US10060696
申请日：2002-01-30
申请人： Gary Brown , Siew Siong Teo , Luan Vu
发明人： Gary Brown , Siew Siong Teo , Luan Vu
IPC分类号： H01H8500
CPC分类号： G11C17/16
摘要： A polysilicon fuse trim read cell utilizes a fuse structure in a single bit memory cell. When the fuse structure is blown, the memory cell can be read and its stored value retained as a digital output. The cell uses no power in the steady state.
摘要翻译：多晶硅熔丝修整读取单元在单个位存储单元中使用熔丝结构。当熔丝结构熔断时，可以读取存储单元并将其存储值保留为数字输出。电池在稳定状态下不使用电源。

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