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11. 发明授权

US07999817B1 Buffering unit to support graphics processing operations 有权
标题翻译：缓冲单元支持图形处理操作
公开(公告)号：US07999817B1
公开(公告)日：2011-08-16
申请号：US11556051
申请日：2006-11-02
申请人： Andrew J. Tao , Vimal S. Parikh , Yan Yan Tang
发明人： Andrew J. Tao , Vimal S. Parikh , Yan Yan Tang
IPC分类号： G06T1/60
CPC分类号： G06T1/00
摘要： An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a memory and a buffering unit that is connected to the memory. The buffering unit is configured to buffer vertex attributes en route to the memory. The buffering unit is configured to coalesce a subset of the vertex attributes to be stored within a common range of addresses in the memory, and the buffering unit is configured to issue a single write request to the memory on behalf of the subset of the vertex attributes.
摘要翻译：描述用于缓冲图形数据的装置和方法。在一个实施例中，图形处理装置包括存储器和连接到存储器的缓冲单元。缓冲单元被配置为缓冲到存储器的途中的顶点属性。缓冲单元被配置为将要存储在存储器中的公共地址范围内的顶点属性的子集合并且缓冲单元被配置为代表顶点属性的子集向存储器发出单个写入请求。

12. 发明申请

US20110069076A1 REGISTER INDEXED SAMPLER FOR TEXTURE OPCODES 有权
标题翻译：用于纹理操作码的注册表索引器
公开(公告)号：US20110069076A1
公开(公告)日：2011-03-24
申请号：US12868586
申请日：2010-08-25
申请人： John Erik LINDHOLM , Yan Yan Tang
发明人： John Erik LINDHOLM , Yan Yan Tang
IPC分类号： G06T11/40
CPC分类号： G06T11/001 , G06T11/40
摘要： One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.
摘要翻译：本发明的一个实施例提出了一种使用索引动态地指定纹理头和纹理采样器的技术。索引对应于在执行着色器程序期间可以是静态的或计算的特定寄存器值。任何纹理操作指令都可以为每个纹理头和纹理采样器指定一个索引值。

13. 发明授权

US07027064B2 Active block write-back from SRAM cache to DRAM 有权
公开(公告)号：US07027064B2
公开(公告)日：2006-04-11
申请号：US10086174
申请日：2002-02-28
申请人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
发明人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
IPC分类号： G09G5/36 , G06F13/00 , G06F12/00
CPC分类号： G09G5/39 , G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/455 , G06T1/60 , G09G2360/121
摘要： An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

14. 发明授权

US08700877B2 Address mapping for a parallel thread processor 有权
标题翻译：并行线程处理器的地址映射
公开(公告)号：US08700877B2
公开(公告)日：2014-04-15
申请号：US12890518
申请日：2010-09-24
申请人： Michael C. Shebanow , Yan Yan Tang , John R. Nickolls
发明人： Michael C. Shebanow , Yan Yan Tang , John R. Nickolls
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0284 , G06F9/3851 , G06F12/0607
摘要： A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.
摘要翻译：一种并行线程处理器中线程地址映射的方法。该方法包括接收与线程组中的第一线程相关联的线程地址; 基于线程地址在线程地址空间的本地窗口内的位置来计算有效地址; 基于有效地址和与第一线程相关联的线程标识符计算与线程组相关联的地址空间中的线程组地址; 以及基于所述线程组地址和线程组标识符计算与所述第一线程相关联的虚拟地址，其中所述虚拟地址用于访问与所述线程地址相关联的存储器中的位置以加载或存储数据。

15. 发明授权

US08266382B1 Cache interface protocol including arbitration and hints 有权
标题翻译：缓存接口协议包括仲裁和提示
公开(公告)号：US08266382B1
公开(公告)日：2012-09-11
申请号：US12650214
申请日：2009-12-30
申请人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
发明人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/28
摘要： One embodiment of the present invention sets forth a technique for arbitrating requests received from one of the multiple clients of an L1 cache and for providing hints to the client to assist in arbitration. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.
摘要翻译：本发明的一个实施例提出了一种用于仲裁从L1高速缓存的多个客户机中的一个接收的请求并且向客户端提供帮助以协助仲裁的技术。 L1缓存服务于具有不同延迟和带宽需求的多个客户端，并且可以被重新配置为为执行多个并行线程的客户端提供存储空间，其中每个存储空间具有不同的范围。

16. 发明授权

US06833834B2 Frame buffer organization and reordering 有权
标题翻译：帧缓冲区组织和重新排序
公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译：图形系统包括帧缓冲器，写地址生成器和像素缓冲器。从帧缓冲器接收到的像素突发可能不是显示顺序。在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。写入地址对应于每个相应像素的突发内的相对显示顺序。突发中的每个像素被存储到像素缓冲器中的其写入地址。这样，突发中的像素以像素缓冲器内的显示顺序存储。

17. 发明授权

US06806883B2 System and method for handling display device requests for display data from a frame buffer 有权
标题翻译：用于处理从帧缓冲器显示数据的显示设备请求的系统和方法
公开(公告)号：US06806883B2
公开(公告)日：2004-10-19
申请号：US10094930
申请日：2002-03-11
申请人： Michael G. Lavelle , Yan Yan Tang
发明人： Michael G. Lavelle , Yan Yan Tang
IPC分类号： G06F1318
CPC分类号： G09G5/363 , G09G5/001 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2360/12
摘要： A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.
摘要翻译：图形系统可以包括帧缓冲器，耦合到访问帧缓冲器中的数据的处理设备，耦合到帧缓冲器的帧缓冲器接口，以及输出控制器，被配置为断言显示数据的请求以提供给显示设备。帧缓冲器接口可以从输出控制器接收对显示数据的请求，并且如果处理设备正在请求访问由显示数据请求所针对的帧缓冲区的一部分，则向帧缓冲器提供对显示数据的请求的延迟。例如，如果帧缓冲器包括多个存储体并且显示数据的请求针对第一存储体，则如果处理设备正在请求访问第一存储体，则帧缓冲器接口可以延迟向帧缓冲器提供对显示数据的请求。

18. 发明授权

US06720969B2 Dirty tag bits for 3D-RAM SRAM 失效
标题翻译： 3D-RAM SRAM的脏标签位
公开(公告)号：US06720969B2
公开(公告)日：2004-04-13
申请号：US09861172
申请日：2001-05-18
申请人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
发明人： Michael G. Lavelle , Ewa M. Kubalska , Yan Yan Tang
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译：描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。在空的存储器循环期间提供了周期性的一级缓存块清理。

19. 发明授权

US09013498B1 Determining a working set of texture maps 有权
标题翻译：确定纹理贴图的工作集
公开(公告)号：US09013498B1
公开(公告)日：2015-04-21
申请号：US12340499
申请日：2008-12-19
申请人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
发明人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
IPC分类号： G09G5/00 , G09G5/37
CPC分类号： G09G5/37 , G06T15/005 , G06T15/04 , G06T2210/36
摘要： A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.
摘要翻译：用于跟踪和报告在图形处理期间计算的细节纹理图层级的系统和方法允许纹理图存储的有效管理。图形处理器跟踪细节值的最小和/或最大预夹紧纹理映射级别，更新存储在存储器中的阵列以报告应用程序使用的最小值和/或最大值。最小值和/或最大值可用于确定加载到图形存储器中的细节的纹理映射级别的活动集合。

20. 发明授权

US08624910B2 Register indexed sampler for texture opcodes 有权
标题翻译：为纹理操作码注册索引采样器
公开(公告)号：US08624910B2
公开(公告)日：2014-01-07
申请号：US12868586
申请日：2010-08-25
申请人： John Erik Lindholm , Yan Yan Tang
发明人： John Erik Lindholm , Yan Yan Tang
IPC分类号： G09G5/00 , G06F13/00 , G06T15/00 , G06T11/40 , G06K9/40 , G06K9/36 , G06K9/54 , G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06T11/001 , G06T11/40
摘要： One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.
摘要翻译：本发明的一个实施例提出了一种使用索引动态地指定纹理头和纹理采样器的技术。索引对应于在执行着色器程序期间可以是静态的或计算的特定寄存器值。任何纹理操作指令都可以为每个纹理头和纹理采样器指定一个索引值。

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