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11. 发明申请

US20090097317A1 Integrated Circuit Having NAND Memory Cell Strings 有权
标题翻译：具有NAND存储器单元串的集成电路
公开(公告)号：US20090097317A1
公开(公告)日：2009-04-16
申请号：US11872655
申请日：2007-10-15
申请人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
发明人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
IPC分类号： G11C16/00 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11565 , H01L27/11568
摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的集成电路和方法。在本发明的实施例中，提供了具有存储单元的集成电路。存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区旁边的沟槽。

12. 发明授权

US06998672B2 Memory cell 失效
标题翻译：存储单元
公开(公告)号：US06998672B2
公开(公告)日：2006-02-14
申请号：US10779557
申请日：2004-02-06
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L29/788
CPC分类号： H01L29/7923
摘要： A memory cell having a source region, a drain region, a source-end control gate, a drain-end control gate, an injection gate arranged between the source-end control gate and the drain-end control gate, a source-end storage element arranged in the source-end control gate, and a drain-end storage element arranged in the drain-end control gate. To program the memory cell, a low electrical voltage is applied to the injection gate, and a high electrical voltage is applied to the control gates.
摘要翻译：具有源极区域，漏极区域，源极端子控制栅极，漏极端子控制栅极，配置在源极端子控制栅极和漏极端子控制栅极之间的注入栅极的存储单元，源极端子存储器排列在源极端控制栅极中的漏极端存储元件，以及布置在漏极端控制栅极中的漏极端存储元件。为了对存储单元进行编程，将低电压施加到注入栅极，并且高电压被施加到控制栅极。

13. 发明授权

US06576948B2 Integrated circuit configuration and method for manufacturing it 有权
标题翻译：集成电路配置及其制造方法
公开(公告)号：US06576948B2
公开(公告)日：2003-06-10
申请号：US09873231
申请日：2001-06-04
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
摘要翻译：集成电路包含平面第一晶体管和二极管。二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。二极管可以配置为隧道二极管。二极管层可以通过热氧化生产。制造二极管只需要一个掩模。电容器可以设置在二极管的上方。电容器的第一电容器电极连接到导电结构。

14. 发明授权

US07767567B2 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US07767567B2
公开(公告)日：2010-08-03
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/3205
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

15. 发明申请

US20080096352A1 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080096352A1
公开(公告)日：2008-04-24
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

16. 发明授权

US07154138B2 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement 失效
标题翻译：晶体管布置，用于操作晶体管布置作为数据存储元件的方法和用于产生晶体管布置的方法
公开(公告)号：US07154138B2
公开(公告)日：2006-12-26
申请号：US10481278
申请日：2002-06-20
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11553 , H01L29/66833 , H01L29/7923
摘要： The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, in between, an electrically insulating layer sequence, wherein two mutually spatially separate sections of the electrically insulating layer sequence in each case serve for the storage of charge carriers.
摘要翻译：本发明涉及具有衬底和垂直晶体管的晶体管装置，其包括：第一电极区域，基本上在其上方布置的第二电极区域，以及沟道区域之间以及沟道区域旁边的栅极区域，以及之间，电绝缘层序列，其中电绝缘层序列的两个相互空间分离的部分在每种情况下用于存储电荷载体。

17. 发明授权

US06639269B1 Electrically programmable memory cell configuration and method for fabricating it 失效
标题翻译：电可编程存储单元配置及其制造方法
公开(公告)号：US06639269B1
公开(公告)日：2003-10-28
申请号：US09648952
申请日：2000-08-25
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11546 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric disposed on sidewalls of the depression. Since the floating gate electrode has a larger area than the channel region, a capacitance formed by a control gate electrode applied on the floating gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region. Two source/drain regions of the transistor likewise adjoin the sidewalls of the depression. An insulation, which is thicker than the first dielectric, isolates the floating gate electrode from the source/drain regions, so that the source/drain regions do not contribute to the coupling ratio.
摘要翻译：存储单元包含平面晶体管，其沟道区设置在衬底中的凹陷的底部。晶体管的浮置栅电极邻接凹陷的底部，底部设置有设置在凹陷的侧壁上的第一电介质。由于浮栅电极具有比沟道区更大的面积，所以由施加在浮置栅电极和浮置栅电极上的控制栅电极形成的电容大于由浮栅电极和沟道区形成的电容。晶体管的两个源极/漏极区同样邻接凹陷的侧壁。比第一电介质厚的绝缘体将浮置栅极与源极/漏极区隔离，使得源极/漏极区域对耦合比没有贡献。

18. 发明授权

US06475866B2 Method for production of a memory cell arrangement 失效
标题翻译：存储单元布置的制造方法
公开(公告)号：US06475866B2
公开(公告)日：2002-11-05
申请号：US09774316
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

19. 发明授权

US06445046B1 Memory cell arrangement and process for manufacturing the same 失效
标题翻译：存储单元布置及其制造方法
公开(公告)号：US06445046B1
公开(公告)日：2002-09-03
申请号：US09331034
申请日：1999-06-15
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul Werner von Basse , Wolfgang Krautschneider
IPC分类号： H01L29772
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
摘要翻译：多个彼此绝缘的存储器单元线路，并且分别包括第一掺杂区域和第二掺杂区域，在该第二掺杂区域和第二掺杂区域之间包含具有电荷载流子阱的材料和多个栅电极的栅极电介质。相邻栅电极的间隔小于栅电极的尺寸。通过将电荷载体引入栅极电介质来存储信息。优选地，通过间隔物技术来制造栅电极。

20. 发明授权

US06399433B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译：一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。在该间隙中形成单元板电极，并在该层中形成沟槽。沟槽达到第一插头表面的最远处，并且填充有绝缘层。该层被删除。形成具有高ε或铁电介质的存储电容器和存储节点电极。电容器设置在身体内和上方的第二平面内。绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

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