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11. 发明申请

US20060179101A1 System and method for providing a decimal multiply algorithm using a double adder 失效
公开(公告)号：US20060179101A1
公开(公告)日：2006-08-10
申请号：US11054567
申请日：2005-02-09
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/496 , G06F2207/4911
摘要： A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

12. 发明授权

US09244654B2 Decimal floating-point quantum exception detection 有权
标题翻译：十进制浮点量子异常检测
公开(公告)号：US09244654B2
公开(公告)日：2016-01-26
申请号：US13544338
申请日：2012-07-09
申请人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
发明人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
IPC分类号： G06F11/00 , G06F7/499 , G06F9/30 , G06F9/38
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点操作数，并对至少一个十进制浮点运算执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

13. 发明申请

US20070061392A1 Fused multiply add split for multiple precision arithmetic 有权
标题翻译：熔融乘法加分多重精度算术
公开(公告)号：US20070061392A1
公开(公告)日：2007-03-15
申请号：US11223641
申请日：2005-09-09
申请人： Guenter Gerwig , Eric Schwarz , Ronald Smith
发明人： Guenter Gerwig , Eric Schwarz , Ronald Smith
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/5443 , G06F2207/3884
摘要： An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order part (H) and a low-order part (L) of an intermediate extended result according to H, L=A*B+C, where A, B are input operands and C an addend. Each H, L part is formatted the same as the format of the input operands, and alignment of the resulting fractions is not affected by alignment of the inputs. The apparatus includes an architecture for suppressing left-alignment of the intermediate extended result, such that input operands for a subsequent A*B+C operation remain right-aligned.
摘要翻译：一种用于执行浮点运算的装置和方法，特别是融合乘法运算。该装置包括一个算术逻辑单元，适用于根据H，L = A * B + C产生中间扩展结果的高阶部分（H）和低阶部分（L），其中A，B为输入操作数和C加法。每个H，L部分的格式与输入操作数的格式相同，所得分数的对齐不受输入对齐的影响。该装置包括用于抑制中间扩展结果的左对齐的结构，使得用于后续A * B + C操作的输入操作数保持右对齐。

14. 发明申请

US20060179099A1 System and method for performing decimal floating point addition 失效
公开(公告)号：US20060179099A1
公开(公告)日：2006-08-10
申请号：US11055231
申请日：2005-02-10
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/4912 , G06F2207/4911
摘要： A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received. The operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. The applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder. The second concurrent calculation includes applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the second assumption results in a second result and includes utilizing the two cycle adder. The third concurrent calculation includes applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the third assumption results in a third result and includes utilizing the two cycle adder. A final result is selected from the first result, the second result and the third result.

15. 发明申请

US20050010631A1 Decimal multiplication using digit recoding 有权
标题翻译：使用数字重新编码的十进制乘法
公开(公告)号：US20050010631A1
公开(公告)日：2005-01-13
申请号：US10616556
申请日：2003-07-10
申请人： Steven Carlough , Eric Schwarz
发明人： Steven Carlough , Eric Schwarz
IPC分类号： G06F7/48 , G06F7/496 , G06F7/52
CPC分类号： G06F7/4824 , G06F7/496
摘要： A system and methodology for decimal multiplication in a microprocessor comprising: a recoder configured to recode decimal digits of a first operand to a corresponding set of {−5 to +5}. The recoder also configured to recode decimal digits of a second operand to a corresponding set of {−5 to +5}. The system also includes a multiplier array of digit multipliers, each digit multiplier configured to generate a partial product of a selected digit of a recoded first operand and a recoded second operand; and an adder array of digit adders, each adder configured to generate a sum of the partial products, wherein a least significant digit of the sum is shifted to a results register, and each adder includes carry feedback.
摘要翻译：一种微处理器中十进制乘法的系统和方法，包括：重新编码器，被配置为将第一操作数的十位数字重新编码为对应的{-5至+5}集合。编码器还配置为将第二操作数的十进制数字重新编码为相应的{-5到+5}集合。该系统还包括数字乘法器的乘法器阵列，每个数字乘法器被配置为生成重新编码的第一操作数的选定位数和重新编码的第二操作数的部分乘积; 和加法器数组加法器阵列，每个加法器被配置为产生部分乘积的和，其中该和的最低有效位被移位到结果寄存器，并且每个加法器包括进位反馈。

16. 发明申请

US20070061388A1 System and method for converting from scaled binary coded decimal into decimal floating point 有权
标题翻译：从缩放二进制编码十进制转换为十进制浮点的系统和方法
公开(公告)号：US20070061388A1
公开(公告)日：2007-03-15
申请号：US11227515
申请日：2005-09-15
申请人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
发明人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , H03M7/04
摘要： A system and method for converting from scaled binary coded decimal (SBCD) into decimal floating point (DFP). The system includes a mechanism for receiving one or more of an exponent part of a SBCD number and a coefficient part of the SBCD number. The system also includes at least one of a mechanism for performing coefficient compression on the coefficient part of the SBCD number to create a coefficient part of a DFP number and a mechanism for performing exponent insertion including inserting the exponent part of the SBCD number into an exponent part of the DFP number.
摘要翻译：从缩放二进制编码十进制（SBCD）转换为十进制浮点（DFP）的系统和方法。该系统包括用于接收SBCD号的指数部分和SBCD号的系数部分中的一个或多个的机构。该系统还包括用于对SBCD号码的系数部分执行系数压缩以创建DFP号码的系数部分的机制和用于执行指数插入的机制中的至少一个，包括将SBCD号码的指数部分插入指数 DFP编号的一部分。

17. 发明申请

US20070061387A1 System and method for converting from decimal floating point into scaled binary coded decimal 有权
标题翻译：从十进制浮点转换为二进制编码十进制的系统和方法
公开(公告)号：US20070061387A1
公开(公告)日：2007-03-15
申请号：US11227481
申请日：2005-09-15
申请人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
发明人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , H03M7/12
摘要： A system and method for converting from decimal floating point (DFP) into scaled binary coded decimal (SBCD). The system includes a mechanism for receiving a DFP number. The system also includes at least one of a mechanism for performing coefficient expansion on the DFP number to create a binary coded decimal (BCD) coefficient part of a SBCD number and a mechanism for performing exponent extraction on the DFP number to create an exponent part of the SBCD number.
摘要翻译：用于从十进制浮点（DFP）转换为缩放二进制编码十进制（SBCD）的系统和方法。该系统包括用于接收DFP号码的机制。该系统还包括用于在DFP号码上执行系数扩展以创建SBCD号码的二进制编码十进制（BCD）系数部分的机制中的至少一个以及用于在DFP号码上执行指数提取以创建指数部分的机构 SBCD号码。

18. 发明申请

US20060190708A1 Multifunction hexadecimal instruction form 有权
公开(公告)号：US20060190708A1
公开(公告)日：2006-08-24
申请号：US11406465
申请日：2006-04-18
申请人： Eric Schwarz , Ronald Smith
发明人： Eric Schwarz , Ronald Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/30014 , G06F9/3001 , G06F9/3802 , G06F9/3836
摘要： A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

19. 发明申请

US20060184603A1 Zero detect in partial sums while adding 审中-公开
标题翻译：零点检测部分和，而添加
公开(公告)号：US20060184603A1
公开(公告)日：2006-08-17
申请号：US11056036
申请日：2005-02-11
申请人： Son Trong , Mark Erle , Bruce Fleischer , Juergen Haess , Michael Kelly , Klaus Kroener , Martin Schmookler , Eric Schwarz
发明人： Son Trong , Mark Erle , Bruce Fleischer , Juergen Haess , Michael Kelly , Klaus Kroener , Martin Schmookler , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/74
摘要： The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to prior art decreases the calculation speed in the multiplier. In order to provide a method and respective electronic circuit, wherein the zero detection is earlier completed, it is proposed to use a leading zero anticipation (LZA) hardware—i.e., an LZA circuit (40), which exists usually anyway in floating point processor adders for calculating the number of leading zeros for operand normalization purposes—for performing a zero detection of the product by aid of the partial results (16, 17) emerging at the output of the Wallace tree of the multiplier. MSB-most and LSB-most margin bits (24, 26) of the partial (16, 17) results which cannot be processed by the LZA circuit (40), are read directly from the final product bit string (22).
摘要翻译：本发明涉及一种用于在计算机处理器的运算单元中执行乘法运算的方法和电路。在其乘数中，为了适当地设置条件代码和溢出状态信息，需要对所得到的产品位串（22）进行零检测。根据现有技术的零检测降低了乘法器中的计算速度。为了提供一种方法和各自的电子电路，其中零检测较早完成，提出使用前导零预期（LZA）硬件即LZA电路（40），其通常在浮点处理器用于计算操作数归一化目的的前导零数量的加法器，用于通过在乘法器的华莱士树的输出处出现的部分结果（16,17）执行零检测。从最终产品位串（22）直接读取不能由LZA电路（40）处理的部分（16,17）结果的MSB最大和LSB最大的边缘位（24,26）。

20. 发明申请

US20060179286A1 System and method for processing limited out-of-order execution of floating point loads 审中-公开
标题翻译：用于处理浮点负载有限次序执行的系统和方法
公开(公告)号：US20060179286A1
公开(公告)日：2006-08-10
申请号：US11054201
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/3838
摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
摘要翻译：用于执行浮点负载有限次序执行的系统。该系统包括构成管道的多个阶段，这些阶段包括早期阶段。该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。如果结果地址等于加载地址，则会发生WAW条件。响应于发生的WAW状态，写入算术指令的结果被抑制。

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