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11. 发明申请

US20120279061A1 CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES 有权
标题翻译：用于可靠的电子基板的集成的堆叠VIAS
公开(公告)号：US20120279061A1
公开(公告)日：2012-11-08
申请号：US13549440
申请日：2012-07-14
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H05K3/40
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
摘要翻译：在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。多个堆叠的通孔具有功能和非功能通孔。

12. 发明授权

US08258410B2 Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权
标题翻译：在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
公开(公告)号：US08258410B2
公开(公告)日：2012-09-04
申请号：US12020534
申请日：2008-01-26
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H05K1/11 , H05K1/09
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
摘要翻译：用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。盘状结构包括支撑多个堆叠的通孔的平板通孔平台。平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。

13. 发明申请

US20090189289A1 EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES 审中-公开
标题翻译：用于电子基板中的可靠堆叠VIAS的嵌入式约束盘
公开(公告)号：US20090189289A1
公开(公告)日：2009-07-30
申请号：US12020561
申请日：2008-01-27
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H01L23/52 , H01L23/535
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/15311
摘要： A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via.
摘要翻译：用于堆叠通孔的衬底通孔结构包括：多个堆叠的通孔，其中每个通孔设置在层站上; 以及围绕至少一个通孔的至少一个约束盘，用于限制基板经由结构的平面内变形。约束盘被嵌入，使得约束盘设置在两层树脂之间。约束盘可以由铜制成。约束盘可以是圆形或正方形。优选地，在约束盘和通孔之间存在电介质间隙。

14. 发明授权

US08440917B2 Method and apparatus to reduce impedance discontinuity in packages 失效
标题翻译：减少封装中阻抗不连续性的方法和装置
公开(公告)号：US08440917B2
公开(公告)日：2013-05-14
申请号：US11942061
申请日：2007-11-19
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

15. 发明申请

US20130075148A1 Method and Apparatus to Reduce Impedance Discontinuity in Packages 有权
标题翻译：减少封装阻抗不连续性的方法和装置
公开(公告)号：US20130075148A1
公开(公告)日：2013-03-28
申请号：US13426892
申请日：2012-03-22
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

16. 发明申请

US20100218891A1 MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC 审中-公开
标题翻译：使用液晶聚合物电介质的多层互连结构
公开(公告)号：US20100218891A1
公开(公告)日：2010-09-02
申请号：US12776771
申请日：2010-05-10
申请人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
发明人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
IPC分类号： C09J5/06
CPC分类号： H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/462 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4641 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1092
摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.
摘要翻译：多层互连结构和形成方法。在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

17. 发明申请

US20090126983A1 Method and Apparatus to Reduce Impedance Discontinuity in Packages 失效
标题翻译：减少封装阻抗不连续性的方法和装置
公开(公告)号：US20090126983A1
公开(公告)日：2009-05-21
申请号：US11942061
申请日：2007-11-19
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/02 , H05K3/10
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

18. 发明授权

US07083901B2 Joining member for Z-interconnect in electronic devices without conductive paste 失效
标题翻译：在没有导电胶的电子设备中连接Z-互连的成员
公开(公告)号：US07083901B2
公开(公告)日：2006-08-01
申请号：US10262724
申请日：2002-10-01
申请人： Frank D. Egitto , Voya Markovich , Thomas R. Miller , Douglas O. Powell , James R. Wilcox
发明人： Frank D. Egitto , Voya Markovich , Thomas R. Miller , Douglas O. Powell , James R. Wilcox
IPC分类号： G03C5/00 , H01K3/00
CPC分类号： H05K3/4069 , H05K3/062 , H05K3/108 , H05K3/423 , H05K3/44 , H05K3/445 , H05K3/4614 , H05K2201/0347 , H05K2201/0355 , H05K2201/0394 , H05K2201/09554 , H05K2203/025 , H05K2203/0384 , H05K2203/0733 , H05K2203/1152 , H05K2203/1461 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T29/49179
摘要： A layer for use in a modular assemblage for supporting ICES is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.
摘要翻译：用于支撑ICES的模块化组件中的层由用于组装的金属触点形成，通过在两层电介质之间制造金属互连构件的夹层; 通过电介质钻孔，停止在与模块底面接合的金属层上; 形成在所述互连构件上停止的盲孔; 并通过通孔的体积电镀金属孔，这两个孔都是盲孔，从而在堆叠形成复杂互连组件的层中形成垂直和水平连接。

19. 发明授权

US06764748B1 Z-interconnections with liquid crystal polymer dielectric films 失效
标题翻译：与液晶聚合物电介质薄膜的Z互连
公开(公告)号：US06764748B1
公开(公告)日：2004-07-20
申请号：US10392637
申请日：2003-03-18
申请人： Donald S. Farquhar , Douglas O. Powell
发明人： Donald S. Farquhar , Douglas O. Powell
IPC分类号： B32B300
CPC分类号： H05K3/4617 , B32B27/36 , H05K3/4688 , H05K2201/0141 , Y10S428/901 , Y10T29/49117 , Y10T156/1052 , Y10T428/24917
摘要： A multilayered stack and method of formation. First and second dielectric layers are formed, respectively including first and second liquid crystal polymer (LCP) dielectric materials, with an electrically conductive plug through the first dielectric layer. A first and second electrical circuitization is formed in direct mechanical contact with a surface of the first and second dielectric layer, respectively, wherein the second electrical circuitization mechanically and electrically contacts an end of the plug, and wherein the plug is fluxlessly soldered to the first electrical circuitization. The first and second dielectric layers and the first electrical circuitization are subjected to a temperature below the lowest nematic-to-isotropic transition temperature of the first and second LCP dielectric materials, for a dwell time and elevated pressure sufficient to cause the first and second LCP dielectric materials to directly bond the second dielectric layer to the first dielectric layer and to the first electrical circuitization.
摘要翻译：多层堆叠和形成方法。形成第一和第二电介质层，分别包括第一和第二液晶聚合物（LCP）电介质材料，其具有通过第一介电层的导电插塞。第一和第二电气电路分别形成为与第一和第二介电层的表面直接机械接触，其中第二电路机械地和电接触插头的端部，并且其中插头被无焊焊接到第一电气化。第一和第二电介质层和第一电路经受低于第一和第二LCP电介质材料的最低向列 - 全向转变温度的温度，停留时间和升高的压力足以引起第一和第二LCP 电介质材料，以将第二电介质层直接接合到第一电介质层和第一电路。

20. 发明授权

US06518516B2 Multilayered laminate 失效
公开(公告)号：US06518516B2
公开(公告)日：2003-02-11
申请号：US10121821
申请日：2002-04-11
申请人： Kim J. Blackwell , Frank D. Egitto , Voya R. Markovich , Manh-Quan T. Nguyen , Douglas O. Powell , David L. Thomas
发明人： Kim J. Blackwell , Frank D. Egitto , Voya R. Markovich , Manh-Quan T. Nguyen , Douglas O. Powell , David L. Thomas
IPC分类号： H01K909
CPC分类号： H01L23/50 , H01L23/5383 , H01L23/5385 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/3025 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4641 , H05K2201/09309 , H05K2201/09536 , Y10T29/49165 , H01L2224/0401
摘要： A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane substructures, wherein a dielectric material of an intervening dielectric layer insulatively separates each pair of successive signal/power plane substructures and (c) a second intermediate layer having microvias and conductive lands.

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