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11. 发明申请

US20070004160A1 TUNABLE SEMICONDUCTOR DIODES 失效
标题翻译：可控半导体二极管
公开(公告)号：US20070004160A1
公开(公告)日：2007-01-04
申请号：US11469582
申请日：2006-09-01
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L21/331
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/8611 , H01L29/8618 , H01L2924/0002 , H01L2924/00
摘要： A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.
摘要翻译：二极管结构制造方法。在P-衬底中，植入N +层。 N +层的开口尺寸影响二极管结构的击穿电压。在N +层上形成N-层。然后，形成P +区域作为二极管结构的阳极。可以在衬底的表面上形成N +区以用作二极管结构的阴极。通过在制造期间改变N +层中的开口的尺寸，可以将二极管结构的击穿电压改变（调谐）至期望的值。

12. 发明申请

US20060048080A1 METHODOLOGY OF QUANTIFICATION OF TRANSMISSION PROBABILITY FOR MINORITY CARRIER COLLECTION IN A SEMICONDUCTOR CHIP 失效
标题翻译：半导体芯片中少数载体收集传输概率的定量方法
公开(公告)号：US20060048080A1
公开(公告)日：2006-03-02
申请号：US10711143
申请日：2004-08-27
申请人： Anne Watson , Steven Voldman
发明人： Anne Watson , Steven Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for computer aided design of semiconductor chips which minimizes sensitivity to latchup is provided. The method evaluates electron transmission, reflection and absorption at geometric shapes that represent components of the semiconductor.
摘要翻译：提供一种半导体芯片的计算机辅助设计方法，其最小化对闭锁的灵敏度。该方法评估了表示半导体元件的几何形状的电子透射，反射和吸收。

13. 发明申请

US20050225910A1 TUNABLE ESD TRIGGER AND POWER CLAMP CIRCUIT 失效
标题翻译： TUNABLE ESD触发器和电源钳位电路
公开(公告)号：US20050225910A1
公开(公告)日：2005-10-13
申请号：US10708911
申请日：2004-03-31
申请人： Andreas Stricker , Steven Voldman
发明人： Andreas Stricker , Steven Voldman
IPC分类号： H01L27/02 , H01L29/737 , H02H9/00
CPC分类号： H01L27/0259 , H01L29/7378 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for the electrostatic discharge protection of integrated circuits. The electrostatic discharge protection circuit, including: an electrostatic discharge protection circuit, comprising: a first bipolar transistor coupled between a first circuit node and a second circuit node, the first bipolar transistor having a non-uniform subcollector region geometry, the first bipolar transistor having a different value for collector to emitter breakdown voltage than a value for collector to emitter breakdown voltage of an otherwise identical bipolar transistor having a uniform subcollector region geometry.
摘要翻译：集成电路的静电放电保护电路及方法。该静电放电保护电路包括：静电放电保护电路，包括：耦合在第一电路节点和第二电路节点之间的第一双极晶体管，所述第一双极晶体管具有不均匀的子集电极区域几何形状，所述第一双极晶体管具有相对于具有均匀子集电极区域几何形状的相同的双极晶体管的集电极至发射极击穿电压的值，集电极至发射极击穿电压的值不同。

14. 发明申请

US20050218921A1 METHOD AND APPLICATION OF PICA (PICOSECOND IMAGING CIRCUIT ANALYSIS) FOR HIGH CURRENT PULSED PHENOMENA 失效
标题翻译： PICA（PICOSECOND成像电路分析）用于高电流脉冲激光源的方法与应用
公开(公告)号：US20050218921A1
公开(公告)日：2005-10-06
申请号：US10814962
申请日：2004-03-31
申请人： Naoko Sanda , Steven Voldman , Alan Weger
发明人： Naoko Sanda , Steven Voldman , Alan Weger
IPC分类号： G01R31/00 , G01R31/28 , G01R31/308 , G01R31/311 , G06F17/50 , H01L21/66 , G01R31/26
CPC分类号： G01R31/308
摘要： A method, system and apparatus are provided for operating a Picosecond Imaging Circuit Analysis (PICA)/high current source system include applying pulses from a high current pulse source to a Device Under Test (DUT). A photosensor detects photon emissions from the DUT. Signals from the photosensor are used to map photon emissions from the DUT. Data processing means relate the photon emissions to specific features of the DUT.
摘要翻译：提供了一种用于操作Picosecond成像电路分析（PICA）/高电流源系统的方法，系统和装置，包括将来自高电流脉冲源的脉冲施加到被测设备（DUT）。光电传感器检测来自DUT的光子发射。来自光电传感器的信号用于映射DUT的光子发射。数据处理手段将光子发射与DUT的特定特征相关联。

15. 发明申请

US20050161743A1 ELECTROSTATIC DISCHARGE INPUT AND POWER CLAMP CIRCUIT FOR HIGH CUTOFF FREQUENCY TECHNOLOGY RADIO FREQUENCY (RF) APPLICATIONS 失效
标题翻译：用于高切割频率技术的静电放电输入和电源钳位电路无线电频率（RF）应用
公开(公告)号：US20050161743A1
公开(公告)日：2005-07-28
申请号：US10707954
申请日：2004-01-28
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L27/02 , H01L29/06 , H01L29/737 , H01L21/331 , H01L23/62
CPC分类号： H01L27/0259 , H01L29/0657 , H01L29/7378 , H01L2924/0002 , H01L2924/00
摘要： A SiGe ESD (electrostatic discharge) power clamp circuit having a forward biased trigger device fabricated in a given technology and a clamp transistor preferably comprising a high frequency cutoff SiGe npn transistor, wherein the trigger device has a turn-on voltage which is below the Johnson Limit breakdown voltage of the highest frequency device fabricated in the given technology.
摘要翻译：具有以给定技术制造的正向偏置触发器件和优选地包括高频截止SiGe npn晶体管的钳位晶体管的SiGe ESD（静电放电）功率钳位电路，其中所述触发器件具有低于Johnson的导通电压限制在给定技术中制造的最高频率器件的击穿电压。

16. 发明申请

US20050121741A1 Apparatus and method for electronic fuse with improved ESD tolerance 有权
标题翻译：具有改善ESD耐受性的电子熔断器的装置和方法
公开(公告)号：US20050121741A1
公开(公告)日：2005-06-09
申请号：US11004846
申请日：2004-12-07
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L21/44 , H01L21/82 , H01L23/525 , H01L27/02 , H01L29/00
CPC分类号： H01L23/5256 , H01L27/0248 , H01L2924/0002 , Y10T29/49107 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , H01L2924/00
摘要： Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.
摘要翻译：通过在绝缘体的表面上提供与导电区域相邻的至少一个非导电区域，在电子熔断器中增加对ESD的耐受性。这种布置降低了在大电流应用中施加在绝缘体上的热应力。在多个导电和相邻的非导电区域设置在绝缘体上的情况下，保险丝可以在离散的步骤中失效，从而提供良好限定且易于检测到的吹扫状态的接收，以及提供规定电阻值之间的电阻的逐步增加。

17. 发明授权

US07709930B2 Tuneable semiconductor device with discontinuous portions in the sub-collector 失效
标题翻译：在子集电极中具有不连续部分的可调谐半导体器件
公开(公告)号：US07709930B2
公开(公告)日：2010-05-04
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

18. 发明授权

US07705426B2 Integration of a SiGe- or SiGeC-based HBT with a SiGe- or SiGeC-strapped semiconductor device 有权
标题翻译：基于SiGe或SiGeC的HBT与SiGe或SiGeC带状半导体器件的集成
公开(公告)号：US07705426B2
公开(公告)日：2010-04-27
申请号：US11558480
申请日：2006-11-10
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L29/10 , H01L29/737
CPC分类号： H01L27/0635 , H01L21/8249 , H01L27/10894 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.
摘要翻译：本发明提供一种集成半导体器件，其包括半导体衬底，含有位于半导体衬底的第一区域中的异质结双极晶体管（HBT）的第一器件，其中HBT包括含有SiGe的第一部分的基极区域或 SiGeC层和位于半导体衬底的第二区域中的第二器件，其中第二器件包括含有SiGe或SiGeC层的第二部分的互连。在本发明的具体实施例中，第二器件是包括通过SiGe或SiGeC层的第二部分电连接在一起的沟槽电容器和场效应晶体管（FET）的存储器件。或者，第二器件是沟槽偏置PNPN可硅可控整流器（SCR）。本发明还提供了一种新颖的可逆编程装置或由新颖的沟槽偏置SCR装置形成的新型存储装置。

19. 发明申请

US20070181972A1 INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT 失效
标题翻译：集成电路结构与硅锗电容器作为本地互连和/或联系
公开(公告)号：US20070181972A1
公开(公告)日：2007-08-09
申请号：US11275481
申请日：2006-01-09
申请人： Steven Voldman
发明人： Steven Voldman
IPC分类号： H01L29/00
CPC分类号： H01L27/1104 , H01L21/28525 , H01L21/76895 , H01L27/10867 , H01L27/11 , H01L29/66181
摘要： Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
摘要翻译：公开了各自具有并入作为局部互连和/或电接触的硅锗膜的集成电路结构。这些集成电路结构在器件之间提供改进的局部互连和/或增加对器件的电容，而不显着增加结构表面面积或功率要求。具体地，公开了将硅锗膜作为一个或多个以下特征的集成电路结构：作为器件之间的局部互连; 作为与器件（例如，深沟槽电容器，晶体管的源极/漏极区域等）的电接触; 作为与深沟槽电容器的电接触和深沟槽电容器与另一器件之间的局部互连的两者; 并且作为与深沟槽电容器的电接触以及作为深沟槽电容器和其他器件之间的局部互连的两者。

20. 发明申请

US20070023811A1 VERTICAL P-N JUNCTION DEVICE AND METHOD OF FORMING SAME 有权
标题翻译：垂直P-N连接装置及其形成方法
公开(公告)号：US20070023811A1
公开(公告)日：2007-02-01
申请号：US11161239
申请日：2005-07-27
申请人： Benjamin Voegeli , Steven Voldman
发明人： Benjamin Voegeli , Steven Voldman
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0635 , H01L27/0664 , H01L29/66136 , H01L29/66242 , H01L29/861
摘要： A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a semiconductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.
摘要翻译：公开了一种P-N结装置及其形成方法。 P-N结器件可以包括P-N二极管，PiN二极管或晶闸管。 P-N结器件可以具有单晶或多晶凸起的阳极。在一个实施例中，P-N结器件导致凸起的多晶硅锗（SiGe）阳极。在另一个实施例中，P-N结器件包括第一端子（阳极），其包括位于衬底的上表面上方的半导体层和位于衬底中的剩余结构，第一端子位于隔离区域中的开口上方; 以及位于与所述第一端子相邻的隔离区域中的开口上方的第二端子（阴极接触件）。后一个实施例降低了寄生电阻和电容，并且减小了阴极注入区域的所需尺寸，因为阴极接触处于与阳极相同的STI开口内。

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