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11. 发明申请

US20080133180A1 WEIGHTED EVENT COUNTING SYSTEM AND METHOD FOR PROCESSOR PERFORMANCE MEASUREMENTS 有权
标题翻译：加权事件计数系统和处理器性能测量方法
公开(公告)号：US20080133180A1
公开(公告)日：2008-06-05
申请号：US11951310
申请日：2007-12-05
申请人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller , Karthick Rajamani , Freeman Leigh Rawson , Juan C. Rubio
发明人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller , Karthick Rajamani , Freeman Leigh Rawson , Juan C. Rubio
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
摘要翻译：用于处理器性能测量的加权事件计数系统和方法提供低延迟和低误差性能测量能力。加权性能计数器根据从处理器中的功能单元提供的多个事件信号累加性能计数。根据具有处理器性能的每个事件之间的相关性，将不同的权重应用于事件信号。权重可以由可编程寄存器提供，从而可以在程序控制下调整权重。事件信号可以被组合以减少事件信号集合的位宽，其中在组合结果的单个字段中合并相互排斥的事件和具有根据子总计合并的相同权重的事件。权重应用于组合结果，用于更新性能计数。电源管理软件或硬件可以使用性能计数来对处理器的运行参数进行调整。

12. 发明授权

US08943341B2 Minimizing power consumption for fixed-frequency processing unit operation 有权
标题翻译：降低固定频率处理单元运行的功耗
公开(公告)号：US08943341B2
公开(公告)日：2015-01-27
申请号：US13443301
申请日：2012-04-10
申请人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
发明人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.
摘要翻译：提供了一种用于最小化固定频率处理单元的操作的功耗的机构。在与固定频率处理单元接合节流的时间窗中计数多个时隙。将节流作业的时间间隔除以时间窗口内的总时间数，从而产生性能损失（PLOSS）值。确定确定与固定频率处理单元相关联的（PLOSS）值是否大于允许的性能损失（APLOSS）值。响应于PLOSS值小于或等于APLOSS值，开始向固定频率处理单元提供的电压的降低。

13. 发明授权

US08566618B2 Reliable setting of voltage and frequency in a microprocessor 有权
标题翻译：微处理器中电压和频率的可靠设置
公开(公告)号：US08566618B2
公开(公告)日：2013-10-22
申请号：US12573284
申请日：2009-10-05
申请人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
发明人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended.
摘要翻译：管理与一个或多个电压变化和一个或多个频率变化相关联的操作。电压变化请求和频率变化请求与动态电压和频率缩放（DVFS）操作相关联。 DVFS操作由处理器发送以由一个或多个直流组件执行。与该一个或多个电压变化相关联的序列和与一个或多个频率变化相关联的序列由系统检测。这些序列被动态地修改以允许插入额外的电压变化，由此额外的电压变化指示完成一个或多个先前的电压变化请求。完成电压变化请求使得能够处理一个或多个后续电压变化请求。当电压变化请求未成功完成时，一个或多个未来的电压变化被暂停。

14. 发明申请

US20120043982A1 CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION 有权
标题翻译：具有选择性操作模式和单边缘检测的关键路径监视器
公开(公告)号：US20120043982A1
公开(公告)日：2012-02-23
申请号：US12861289
申请日：2010-08-23
申请人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
IPC分类号： G01R31/3187
CPC分类号： G01R31/31725
摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.
摘要翻译：具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如作为对应于关键路径延迟的变化的边缘位置的范围。

15. 发明授权

US07908493B2 Unified management of power, performance, and thermals in computer systems 有权
标题翻译：计算机系统中的功率，性能和热量的统一管理
公开(公告)号：US07908493B2
公开(公告)日：2011-03-15
申请号：US11758798
申请日：2007-06-06
申请人： Andreas Bieswanger , Michael S. Floyd , Soraya Ghiasi , Steven P. Hartman , Thomas W. Keller, Jr. , Hye-Young McCreary , Karthick Rajamani , Freeman L. Rawson, III , Juan C. Rubio , Malcolm S. Ware
发明人： Andreas Bieswanger , Michael S. Floyd , Soraya Ghiasi , Steven P. Hartman , Thomas W. Keller, Jr. , Hye-Young McCreary , Karthick Rajamani , Freeman L. Rawson, III , Juan C. Rubio , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3203
摘要： A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.
摘要翻译：提供了一种统一管理计算机系统的功率，性能和热量的机制。该机制包含了以综合方式有效地解决管理计算系统的所有方面的元素，而不是独立的。该机制采用基础设施进行实时测量反馈，用于调节系统活动的基础设施，组件操作级别和环境控制，用于保证响应/抢先动作的专用控制结构以及交互和集成组件。该机制为用户级交互提供接口。该机制还采用了多个时间尺度来解决功率/热问题的方法。此外，该机制采用综合方法提高效率，而不是以单独的方式处理单个问题，而不是将功率/热问题的不同方面进行处理。

16. 发明授权

US07340378B1 Weighted event counting system and method for processor performance measurements 失效
标题翻译：加权事件计数系统和处理器性能测量方法
公开(公告)号：US07340378B1
公开(公告)日：2008-03-04
申请号：US11565106
申请日：2006-11-30
申请人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller, Jr. , Karthick Rajamani , Freeman Leigh Rawson, III , Juan C. Rubio
发明人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller, Jr. , Karthick Rajamani , Freeman Leigh Rawson, III , Juan C. Rubio
IPC分类号： G06F19/00
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
摘要翻译：用于处理器性能测量的加权事件计数系统和方法提供低延迟和低误差性能测量能力。加权性能计数器根据从处理器中的功能单元提供的多个事件信号累加性能计数。根据具有处理器性能的每个事件之间的相关性，将不同的权重应用于事件信号。权重可以由可编程寄存器提供，从而可以在程序控制下调整权重。事件信号可以被组合以减少事件信号集合的位宽，其中在组合结果的单个字段中合并相互排斥的事件和具有根据子总计合并的相同权重的事件。权重应用于组合结果，用于更新性能计数。电源管理软件或硬件可以使用性能计数来对处理器的运行参数进行调整。

17. 发明授权

US09164563B2 Processor noise mitigation using differential critical path monitoring 有权
标题翻译：使用差分关键路径监控的处理器噪声抑制
公开(公告)号：US09164563B2
公开(公告)日：2015-10-20
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/28 , G06F1/26 , G06F11/30
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

18. 发明授权

US08650431B2 Non-disruptive hardware change 失效
标题翻译：无中断硬件的变化
公开(公告)号：US08650431B2
公开(公告)日：2014-02-11
申请号：US12862492
申请日：2010-08-24
申请人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
发明人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.
摘要翻译：一种用于在不中断在数据处理系统上执行的处理的情况下改变数据处理系统中的硬件的方法，系统和计算机程序产品。可能需要对数据处理系统中的所选部分硬件进行硬件更改，例如修复硬件错误或实现系统更新。响应于要求硬件对硬件的所选部分的改变的确定，所选择的部分执行的处理从硬件的所选部分移动到硬件的替代部分。硬件更改应用于硬件的选定部分。在应用硬件更改之后，硬件的所选部分返回供数据处理系统使用。

19. 发明申请

US20130268786A1 Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation 审中-公开
公开(公告)号：US20130268786A1
公开(公告)日：2013-10-10
申请号：US13611210
申请日：2012-09-12
申请人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
发明人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.

20. 发明申请

US20130088374A1 SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH COMPARATOR INPUT TOGGLING 失效
标题翻译：具有比较器输入功能的数字转换器的连续逼近模拟
公开(公告)号：US20130088374A1
公开(公告)日：2013-04-11
申请号：US13270983
申请日：2011-10-11
申请人： Ann H. Chen , Michael S. Floyd , Birgit Schubert , Michael A. Sperling
发明人： Ann H. Chen , Michael S. Floyd , Birgit Schubert , Michael A. Sperling
IPC分类号： H03M1/38
CPC分类号： H03M1/0663 , H03M1/46
摘要： A successive approximation analog-to-digital converter (SA-ADC) includes a reference generator configured to output a first voltage and a second voltage; a comparator, the comparator having a positive input and a negative input thereto, the comparator being configured to receive the first voltage and the second voltage; and a comparator input toggle located between the reference generator and the comparator, wherein the comparator input toggle is configured to receive the first and second voltages from the reference generator and provide the first and second voltages to the comparator, wherein the comparator input toggle is further configured to switch between a first position, in which the first voltage is connected to the positive input, and the second voltage is connected to the negative input, and a second position, in which the second voltage is connected to the positive input, and the first voltage is connected to the negative input.
摘要翻译：逐次逼近模数转换器（SA-ADC）包括被配置为输出第一电压和第二电压的参考发生器; 比较器，其具有正输入和负输入，所述比较器被配置为接收所述第一电压和所述第二电压; 以及位于所述参考发生器和所述比较器之间的比较器输入触发器，其中所述比较器输入触发器被配置为从所述参考发生器接收所述第一和第二电压并将所述第一和第二电压提供给所述比较器，其中所述比较器输入触发器进一步被配置为在所述第一位置与所述正输入端连接所述第一电压并且所述第二电压连接到所述负输入端的第二位置和所述第二电压连接到所述正输入端的第二位置，第一个电压连接到负输入。

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