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11. 发明授权

US07586130B2 Vertical field effect transistor using linear structure as a channel region and method for fabricating the same 有权
标题翻译：使用线性结构作为沟道区域的垂直场效应晶体管及其制造方法
公开(公告)号：US07586130B2
公开(公告)日：2009-09-08
申请号：US11344574
申请日：2006-02-01
申请人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
发明人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
IPC分类号： H01L29/732
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/1606 , H01L29/42384 , H01L29/7781 , H01L29/78642 , Y10S977/938
摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
摘要翻译：垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。晶体管还包括在上电极和下电极之间的电介质部分。上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。有源区域位于上电极的伸出部分正下方。

12. 发明授权

US07091099B2 Bipolar transistor and method for fabricating the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07091099B2
公开(公告)日：2006-08-15
申请号：US10807307
申请日：2004-03-24
申请人： Teruhito Ohnishi , Koichiro Yuki , Tsuneichiro Sano , Tohru Saitoh , Ken Idota , Takahiro Kawashima , Shigeki Sawada
发明人： Teruhito Ohnishi , Koichiro Yuki , Tsuneichiro Sano , Tohru Saitoh , Ken Idota , Takahiro Kawashima , Shigeki Sawada
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
摘要翻译：双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极，和发射极层。在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

13. 发明授权

US5663516A Karaoke apparatus having physical model sound source driven by song data 失效
标题翻译：具有由歌曲数据驱动的物理模型声源的卡拉OK装置
公开(公告)号：US5663516A
公开(公告)日：1997-09-02
申请号：US659262
申请日：1996-06-06
申请人： Takahiro Kawashima
发明人： Takahiro Kawashima
IPC分类号： G10H7/08 , G10H1/00 , G10H1/36 , G10H5/00 , G10K15/04 , G09B5/00
CPC分类号： G10H5/007 , G10H1/361 , G10H1/365 , G10H2220/011 , G10H2240/125 , G10H2240/245 , G10H2250/515 , G10H2250/535
摘要： In a karaoke apparatus responsive to a request for producing a karaoke accompaniment according to performance data, a sound source of a physical model type is controlled according to shape data which characterizes an acoustic vibration of a model musical instrument for electrically simulating the acoustic vibration to synthesize a tone waveform as if created by the model musical instrument, and is driven according to performance data for sequentially processing the tone waveform to produce the karaoke accompaniment. A distributor is settable with the shape data for feeding the sound source with the set physical data. A memory stores a plurality of items of performance data and a plurality of types of shape data in correspondence with each other. A driver is responsive to the request for retrieving from the memory a requested item of the performance data to sequentially feed the same to the sound source to thereby commence the karaoke accompaniment, and operates before the karaoke accompaniment is commenced for retrieving from the memory a corresponding type of the shape data to set the same into the distributor so that the sound source can be fed with a pair of the requested item of the performance data and the corresponding type of the shape data. A downloader downloads new types of the shape data into the memory to update a file containing a plurality of old types of the shape data.
摘要翻译：在响应于根据性能数据产生卡拉OK伴奏的请求的卡拉OK装置中，根据表征用于电气模拟声振动的模型乐器的声振动的形状数据来控制物理模型类型的声源，以合成音乐波形，如同由模特乐器创建的，并且根据用于顺序处理音调波形的演奏数据被驱动以产生卡拉OK伴奏。分配器可以用形状数据进行设置，用于将声源馈送到设定的物理数据。存储器存储多个对应的演奏数据和多种形状数据。驾驶员响应于从存储器检索演奏数据的所请求的项目的请求，以顺序地将其提供给声源，从而开始卡拉OK伴奏，并且在卡拉OK伴奏开始之前操作以从存储器检索对应的形状数据的类型将其设置为分配器，使得声源可以被馈送一对所需的演奏数据项和相应类型的形状数据。下载器将形式数据的新类型下载到存储器中以更新包含多种旧类型的形状数据的文件。

14. 发明授权

US5518408A Karaoke apparatus sounding instrumental accompaniment and back chorus 失效
标题翻译：卡拉OK仪器伴奏伴奏和背部合唱
公开(公告)号：US5518408A
公开(公告)日：1996-05-21
申请号：US222475
申请日：1994-04-01
申请人： Takahiro Kawashima , Shuichi Matsumoto
发明人： Takahiro Kawashima , Shuichi Matsumoto
IPC分类号： G09B15/00 , G10H1/36 , G10H7/02 , G09B5/00
CPC分类号： G10H7/02 , G09B15/00 , G10H1/361 , G10H2210/251 , G10H2240/056 , G10H2240/125 , G10H2240/245 , G10H2250/595
摘要： A karaoke apparatus is comprised of a data supply, a tone generator, an ADPCM decoder and a pitch shifter for sounding a requested karaoke song containing an instrumental accompaniment and a back chorus. The data supply supplies an ADPCM data representative of a phrase back chorus and being compressed by a variable compression condition, and supplies a song data containing accompaniment information prescriptive of an instrumental accompaniment, additional information prescriptive of a common back chorus and decoding information indicative of the variable compression condition of the ADPCM data, and further supplies key information which determines a pitch shift of the karaoke song. The tone generator processes the accompaniment information and the additional information to generate a first audio signal effective to sound synthesized tones of the instrumental accompaniment and the common back chorus. The ADPCM decoder operates in synchronization with the tone generator to decode the ADPCM data according to the decoding information for reproducing a second audio signal effective to sound the phrase back chorus concurrently with the instrumental accompaniment. The pitch shifter processes the second audio signal according to the key information to carry out the pitch shift of the phrase back chorus.
摘要翻译：卡拉OK装置包括数据提供器，音调发生器，ADPCM解码器和用于发出包含乐器伴奏和后合唱的所请求的卡拉OK歌曲的音调移位器。数据电源提供表示短语背部合唱并被可变压缩条件压缩的ADPCM数据，并提供包含伴奏伴奏辅助信息的歌曲数据，规定的公共背部合唱的附加信息以及指示 ADPCM数据的可变压缩条件，并且进一步提供确定卡拉OK歌曲的音高偏移的键信息。乐音发生器处理伴奏信息和附加信息以产生有效声音乐器伴奏和公共背部合唱的合成音调的第一音频信号。 ADPCM解码器与乐音发生器同步地操作，以根据用于再现与乐器伴奏同时发声的短语背部合唱的第二音频信号的解码信息解码ADPCM数据。音调移位器根据密钥信息处理第二音频信号以执行短语背部合唱的音调偏移。

15. 发明授权

US09048220B2 Method of crystallizing silicon thin film and method of manufacturing silicon thin-film transistor device 有权
标题翻译：硅薄膜的结晶方法和硅薄膜晶体管器件的制造方法
公开(公告)号：US09048220B2
公开(公告)日：2015-06-02
申请号：US13228804
申请日：2011-09-09
申请人： Tomohiko Oda , Takahiro Kawashima
发明人： Tomohiko Oda , Takahiro Kawashima
IPC分类号： H01L21/00 , H01L21/84 , H01L29/423 , H01L29/66 , H01L29/786 , H01L27/12
CPC分类号： H01L29/42384 , H01L27/1281 , H01L27/1285 , H01L29/66765 , H01L29/78678
摘要： A method of crystallizing a silicon thin film, which enables uniforming the size of a crystalline grain of the silicon thin film, includes: a second process of stacking, on a substrate, a first gate electrode having a first reflectivity; a third process of stacking a second gate electrode on the first gate electrode, the second gate electrode having a second reflectivity lower than the first reflectivity and including a top face having an area smaller than an area of the top face of the first gate electrode; a fourth process of stacking a gate insulation film to cover a first region and a second region; a fifth process of stacking a noncrystalline silicon thin film on the stacked gate insulation film; and a sixth process of crystallizing the noncrystalline silicon thin film by irradiating the noncrystalline silicon thin film from above with a laser beam.
摘要翻译：使硅薄膜的晶粒尺寸均匀化的硅薄膜的结晶方法包括：在基板上堆叠具有第一反射率的第一栅电极的第二工序; 在所述第一栅电极上层叠第二栅电极的第三工序，所述第二栅电极具有比所述第一反射率低的第二反射率，并且包括具有小于所述第一栅电极的顶面的面积的面的顶面; 堆叠栅极绝缘膜以覆盖第一区域和第二区域的第四工艺; 堆叠栅极绝缘膜上的非晶硅薄膜的第五工序; 以及通过用激光束从上方照射非晶硅薄膜来使非晶硅薄膜结晶的第六工序。

16. 发明授权

US08106382B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08106382B2
公开(公告)日：2012-01-31
申请号：US12305824
申请日：2007-06-18
申请人： Tohru Saitoh , Takahiro Kawashima
发明人： Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L29/66
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/41733 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×1019 cm−3 or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.
摘要翻译：连接到多个半导体纳米结构中的至少一个半导体纳米结构103的一部分的源电极105，连接到半导体纳米结构103的另一部分的漏电极106和能够控制半导体纳米结构103的导电的栅电极102 包括半导体纳米结构103。半导体纳米结构103包括具有相对低的掺杂浓度的低浓度区域108和具有比低浓度区域108的掺杂浓度更高的掺杂浓度的一对高浓度区域107并且连接到低浓度区域108的两端。高浓度区域107的掺杂浓度为1×1019cm-3以上; 低浓度区域108的长度比沿源极电极105至漏电极106的方向的栅电极102的长度短; 并且栅电极102的长度比源电极105和漏电极106之间的间隙短。

17. 发明申请

US20110260789A1 VARIABLE GAIN AMPLIFIER CIRCUIT 有权
标题翻译：可变增益放大器电路
公开(公告)号：US20110260789A1
公开(公告)日：2011-10-27
申请号：US12909763
申请日：2010-10-21
申请人： Takahiro Kawashima , Rui Kurihara
发明人： Takahiro Kawashima , Rui Kurihara
IPC分类号： H03F1/34
CPC分类号： H03G1/0088 , G11B7/13 , H03F3/087 , H03F3/45475 , H03F2203/45526
摘要： A variable gain amplifier circuit includes: an operational amplifier having a non-inverting input terminal applied with a predetermined voltage; a feedback resistor having one end connected to an inverting input terminal of the operational amplifier and the other end connected to an output terminal of the operational amplifier; and a variable resistor having one end applied with an input voltage and the other end connected to the inverting input terminal of the operational amplifier.
摘要翻译：可变增益放大器电路包括：具有施加预定电压的非反相输入端的运算放大器; 反馈电阻器，其一端连接到运算放大器的反相输入端子，另一端连接到运算放大器的输出端子; 以及可变电阻器，其一端施加有输入电压，另一端连接到运算放大器的反相输入端。

18. 发明申请

US20110090716A1 DC-DC CONVERTER WITH SNUBBER CIRCUIT 有权
标题翻译：带有SNUBER电路的DC-DC转换器
公开(公告)号：US20110090716A1
公开(公告)日：2011-04-21
申请号：US12999932
申请日：2009-06-15
申请人： Hideki Asuke , Hideharu Takano , Mamoru Tsuruya , Masayoshi Yamamoto , Takahiro Kawashima , Shigeyuki Funabiki
发明人： Hideki Asuke , Hideharu Takano , Mamoru Tsuruya , Masayoshi Yamamoto , Takahiro Kawashima , Shigeyuki Funabiki
IPC分类号： H02M3/335
CPC分类号： H02M3/1584 , H02M1/34 , H02M2001/348
摘要： In order to achieve an object to reduce a surge voltage and suppress noise generation, the present invention provides a DC-DC converter with a snubber circuit, which boosts a voltage Vi of a DC power supply. The snubber circuit includes: a series circuit connected to both ends of a smoothing capacitor Co and including a snubber capacitor Cs and a snubber resistor Rs; a snubber diode Ds1 connected to a node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr1 and an additional winding 1b of a transformer T1 are connected; and a snubber diode Ds2 connected to the node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr2 and an additional winding 2b of a transformer T2 are connected.
摘要翻译：为了实现降低浪涌电压并抑制噪声产生的目的，本发明提供一种具有缓冲电路的DC-DC转换器，其提高DC电源的电压Vi。缓冲电路包括：连接到平滑电容器Co的两端并包括缓冲电容器Cs和缓冲电阻器Rs的串联电路; 连接到缓冲电容器Cs和缓冲电阻器Rs连接的节点的缓冲二极管Ds1以及与变压器T1的电抗器Lr1和附加绕组1b连接的节点; 以及连接到缓冲电容器Cs和缓冲电阻器Rs所连接的节点的缓冲二极管Ds2以及与变压器T2的电抗器Lr2和附加绕组2b连接的节点。

19. 发明申请

US20100224915A1 METHOD FOR PRODUCING SEMICONDUCTOR CHIP, AND FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：用于制造半导体芯片的方法和场效应晶体管及其制造方法
公开(公告)号：US20100224915A1
公开(公告)日：2010-09-09
申请号：US12159352
申请日：2007-01-12
申请人： Takahiro Kawashima , Tohru Saitoh , Tohru Nakagawa , Hideo Torii
发明人： Takahiro Kawashima , Tohru Saitoh , Tohru Nakagawa , Hideo Torii
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336
CPC分类号： H01L27/1266 , H01L21/8221 , H01L27/0688 , H01L27/1203 , H01L27/1285 , H01L27/1292
摘要： According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).
摘要翻译：根据本发明的用于制造半导体片的方法，首先通过在衬底（10）上层叠牺牲层（11）和半导体层（12）来形成至少两个半导体层（12） 10），并重复该堆叠。接下来，通过蚀刻部分牺牲层（11）和部分半导体层（12）将半导体层（12）分割成多个。然后，通过去除牺牲层（11）将片与衬底分离。

20. 发明授权

US07719031B2 Heterojunction biploar transistor and method for manufacturing same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07719031B2
公开(公告)日：2010-05-18
申请号：US10564085
申请日：2004-07-06
申请人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
发明人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
IPC分类号： H01L29/74
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
摘要翻译：双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。外部基底形成层113的厚度不小于40nm。

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