专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07023758B2 Low power manager for standby operation of a memory system 有权
标题翻译：低功耗管理器用于存储系统的待机操作
公开(公告)号：US07023758B2
公开(公告)日：2006-04-04
申请号：US11205565
申请日：2005-08-17
申请人： David R. Hanson , Gregory J Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
发明人： David R. Hanson , Gregory J Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译：存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线司机。具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

12. 发明授权

US06795962B1 Machine independent debugger 有权
标题翻译：机器独立调试器
公开(公告)号：US06795962B1
公开(公告)日：2004-09-21
申请号：US09475805
申请日：1999-12-30
申请人： David R. Hanson
发明人： David R. Hanson
IPC分类号： G06F944
CPC分类号： G06F11/362
摘要： The present invention teaches a source-level debugger that defines symbol tables with a grammar. A grammar interface component is used by the compiler to automate portions of the debugger to construct and write the symbol table in a grammar thus simplifying the compiler. The grammar interface component is used by the debugger during execution of the target to read and decode the symbol table, thus simplifying the debugger. Using a grammar to specify the symbol table also documents the symbol table concisely and emphasizes that symbol tables are data structures, not file formats. Many of the pitfalls of working with low-level file formats can be avoided by focusing instead on grammar-based high-level data structures and automating the implementation details. Management of breakpoints is divided by splitting the nub into a client nub that is local to the target, a server nub that is local to the debugger. The management of breakpoints is localized to the client nub, thus saving communication time between the client nub and the server nub in support of breakpoint processing.
摘要翻译：本发明教导了用语法定义符号表的源级调试器。编译器使用语法接口组件来自动化调试器的一部分，以便在语法中构造和写入符号表，从而简化了编译器。语法接口组件在执行目标时由调试器用于读取和解码符号表，从而简化了调试器。使用语法指定符号表也简洁地记录符号表，并强调符号表是数据结构，而不是文件格式。使用低级文件格式的许多陷阱可以通过将重点放在基于语法的高级数据结构和自动化实现细节上来避免。断点的管理是通过将nub拆分为本地的客户端标签来划分的目标，是调试器本地的服务器nub。断点的管理被本地化到客户端nub，从而节省了客户端nub和服务器nub之间的通信时间，以支持断点处理。

13. 发明授权

US06292402B1 Prefetch write driver for a random access memory 失效
标题翻译：为随机存取存储器预取写入驱动程序
公开(公告)号：US06292402B1
公开(公告)日：2001-09-18
申请号：US09456589
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C1604
CPC分类号： G11C7/1072 , G11C7/1078
摘要： A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.
摘要翻译：用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。数据级和使能级可以各自包括两个或多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。当数据通过数据阶段时，相应的使能状态通过使能阶段。如果使能状态指示要将数据级中的数据写入阵列，则将数据传送到RAM阵列。

14. 发明授权

US6115308A Sense amplifier and method of using the same with pipelined read, restore and write operations 有权
标题翻译：感应放大器和使用流水线读取，恢复和写入操作的方法
公开(公告)号：US6115308A
公开(公告)日：2000-09-05
申请号：US335092
申请日：1999-06-17
申请人： David R. Hanson , Toshiaki Kirihata
发明人： David R. Hanson , Toshiaki Kirihata
IPC分类号： G11C11/413 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/419 , G11C7/00 , G11C7/02
CPC分类号： G11C7/1039 , G11C7/06
摘要： A method of performing overlapping operations with a memory device may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. The method may include applying a first equalize signal and second equalize signal to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines, applying a switch signal to the sense amplifier circuit to connect the data bus lines to a read data bus, and changing a state of the first equalize signal such that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.
摘要翻译：与存储器件执行重叠操作的方法可以具有读出放大器电路和连接到读出放大器电路的两个驱动器。两条数据总线可以连接到读出放大器电路以接收数据信号。该方法可以包括将第一均衡信号和第二均衡信号施加到读出放大器电路，以允许读出放大器电路跨数据总线接收数据信号，将开关信号施加到读出放大器电路以连接数据总线读取数据总线，并且改变第一均衡信号的状态，使得数据总线线路接收新数据或数据总线线路均等于预定电压，同时数据位于读数据总线上并且能够被读。

15. 发明授权

US5920764A Process for restoring rejected wafers in line for reuse as new 失效
标题翻译：恢复被拒绝的晶片在线再利用的过程是新的
公开(公告)号：US5920764A
公开(公告)日：1999-07-06
申请号：US940723
申请日：1997-09-30
申请人： David R. Hanson , Hance H. Huston, III , Kris V. Srikrishnan
发明人： David R. Hanson , Hance H. Huston, III , Kris V. Srikrishnan
IPC分类号： H01L21/302 , H01L21/324 , H01L21/762 , H01L21/00
CPC分类号： H01L21/02032 , H01L21/324 , H01L21/76254 , Y10S438/928 , Y10S438/959 , Y10S438/977
摘要： A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.
摘要翻译：适用于将缺陷或拒绝的半导体晶片恢复到无缺陷形式的工艺使用了蚀刻剂和Smart-Cut TM工艺的变型。由于使用Smart-Cut TM工艺的变化，可以去除扩散区而不会明显影响半导体晶圆的规格。因此，有缺陷或被拒绝的晶片可以恢复到用于半导体制造的原始状态。

16. 发明授权

US08176283B1 Permissions of objects in hosted storage 有权
标题翻译：托管存储中对象的权限
公开(公告)号：US08176283B1
公开(公告)日：2012-05-08
申请号：US13245488
申请日：2011-09-26
申请人： David R. Hanson , Erkki Ville Juhani Aikas
发明人： David R. Hanson , Erkki Ville Juhani Aikas
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1416 , G06F21/00 , G06F21/6218 , G06F2221/2141
摘要： A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.
摘要翻译：数据对象存储在托管存储系统中，并且包括指定存储在托管存储系统中的数据对象的访问权限的访问控制列表。托管存储系统向被托管存储系统耦合的多个客户端提供托管存储。接收存储第二数据对象的请求。该请求包括一个指示符，即存储在托管存储系统中的第一数据对象应被用作第二数据对象的访问控制列表。第二个数据对象存储在托管存储系统中。第一数据对象被分配为存储在托管存储系统中的第二数据对象的访问控制列表。

17. 发明授权

US07397261B2 Monitoring system for detecting and characterizing classes of leakage in CMOS devices 有权
标题翻译：用于检测和表征CMOS器件泄漏等级的监控系统
公开(公告)号：US07397261B2
公开(公告)日：2008-07-08
申请号：US11380515
申请日：2006-04-27
申请人： Louis Lu-Chen Hsu , Edward R. Pillai , Joseph Natonio , James D. Rockrohr , David R. Hanson
发明人： Louis Lu-Chen Hsu , Edward R. Pillai , Joseph Natonio , James D. Rockrohr , David R. Hanson
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/3008 , G01R31/318577
摘要： A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.
摘要翻译：一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常运行期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。当测试最后一个测试宏时，会扫描泄漏数据。

18. 发明授权

US07136317B1 DRAM with self-resetting data path for reduced power consumption 有权
标题翻译： DRAM具有自动复位数据路径，可降低功耗
公开(公告)号：US07136317B1
公开(公告)日：2006-11-14
申请号：US11161628
申请日：2005-08-10
申请人： David R. Hanson , Hoki Kim
发明人： David R. Hanson , Hoki Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/1051 , G11C7/1069
摘要： A random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.
摘要翻译：随机存取存储器（RAM），例如CMOS集成电路（IC）逻辑芯片上的动态RAM（DRAM）或嵌入式DRAM（eDRAM）。存储器驱动一行连接的全局数据线对以在该对上形成差分信号。同时，全局信号监视线放电以产生反映在该对中的一个上发展的信号的信号。当全局信号监测线路充分放电以指示差信号足够大以感测时，全局检测控制设置全局数据读出放大器，存储器组驱动器关闭，并且全局检测控制启动恢复全局数据线。

19. 发明授权

US07073165B2 Method and apparatus for facilitating execution of applications accepting local path and URL specified file parameters 失效
公开(公告)号：US07073165B2
公开(公告)日：2006-07-04
申请号：US09767768
申请日：2001-01-23
申请人： David R. Hanson
发明人： David R. Hanson
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/4486
摘要： A compiler command is specified and a compiler application or other application is executed. A file name is passed to the application identifying data file input. Special net I/O functionality is included in the net I/O API. This functionality determines whether the file identifier is a URL. If it is not a URL, then standard C API's are used to open, read, and write the file specified. If the identifier is a URL, then Win32 API functions are used to access the Internet and to open, read, and write the file. Thus, the application executes successfully without a download of the remotely stored file input prior to execution.

20. 发明授权

US06954387B2 Dynamic random access memory with smart refresh scheduler 有权
标题翻译：具有智能刷新调度器的动态随机存取存储器
公开(公告)号：US06954387B2
公开(公告)日：2005-10-11
申请号：US10604375
申请日：2003-07-15
申请人： Hoki Kim , Toshiaki Kirihata , David R. Hanson , Gregory J. Fredeman , John Golz
发明人： Hoki Kim , Toshiaki Kirihata , David R. Hanson , Gregory J. Fredeman , John Golz
IPC分类号： G11C11/406 , G11C7/00 , G11C8/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
摘要翻译：在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。每个组的比较器提供一个比较器输出。每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。仲裁器被连接以接收信号中的冲突并提供冲突信号。一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式