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    • 20. 发明申请
    • FRAMEWORK FOR RESULTS INTERPRETATION AND GUIDED REFINEMENT OF SPECIFICATIONS FOR PLC LOGIC VERIFICATION
    • 结果解释和指导对PLC逻辑验证规范的修订框架
    • US20090182442A1
    • 2009-07-16
    • US12352988
    • 2009-01-13
    • NAGARAJAN SETHURAMANSoumen DeChengyin YuanNarahari K. Hunsur
    • NAGARAJAN SETHURAMANSoumen DeChengyin YuanNarahari K. Hunsur
    • G05B19/42G06F17/10
    • G05B19/058G05B2219/13151G05B2219/13188
    • A system and method for interpreting formal verification results of PLC logic code used to control a manufacturing process, or other automated process, where the interpretation process does not require highly skilled technicians having significant experience in computer and mathematical algorithms. The verification process includes providing a verification results summary to check the compliance of the code with respect to the specifications. The verification results summary is analyzed and categorized to determine whether violations or errors are found in the results. The results can be depicted by assertion trees if a direct assertion between the PLC logic and the specifications can be provided. Alternatively, the results can be depicted by a reduced ladder logic if a direct assertion between the PLC logic and the specifications cannot be provided and a simulation is required. The specification refinement suggestions will be provided if the critical variable for violations is identified.
    • 用于解释用于控制制造过程或其他自动化过程的PLC逻辑代码的形式验证结果的系统和方法,其中解释过程不需要具有在计算机和数学算法方面具有丰富经验的高技能技术人员。 验证过程包括提供验证结果摘要,以检查代码是否符合规范。 对验证结果摘要进行分析和分类,以确定结果中是否发现违规或错误。 如果可以提供PLC逻辑和规范之间的直接断言,则可以通过断言树来描述结果。 或者,如果不能提供PLC逻辑和规范之间的直接断言并需要仿真,则结果可以通过减少的梯形逻辑来描述。 如果确定违规的关键变量,将提供规范细化建议。