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11. 发明授权

US06876561B2 Scratchpad memory 失效
标题翻译：便条记忆
公开(公告)号：US06876561B2
公开(公告)日：2005-04-05
申请号：US10726757
申请日：2003-12-03
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.
摘要翻译：集成电路包括随机存取存储器（RAM）存储器和位于一个半导体芯片上的控制器。控制器被耦合以从RAM存储器读取数据并向RAM存储器写入数据。控制器可编程为对存储在RAM中的数据字执行按位运算。

12. 发明授权

US06667920B2 Scratchpad memory 失效
公开(公告)号：US06667920B2
公开(公告)日：2003-12-23
申请号：US10457337
申请日：2003-06-09
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

13. 发明公开

US20240006375A1 PACKAGE ARCHITECTURE WITH COMPUTE BRICKS HAVING VERTICALLY STACKED DIES 审中-公开
公开(公告)号：US20240006375A1
公开(公告)日：2024-01-04
申请号：US17852992
申请日：2022-06-29
申请人： Sagar Suthram , Wilfred Gomes , Pushkar Sharad Ranade , Ravindranath Vithal Mahajan , Debendra Mallik , Omkar G. Karhade , Nitin A. Deshpande , Abhishek A. Sharma , Joshua Fryman , Stephen Morein , Matthew Adiletta
发明人： Sagar Suthram , Wilfred Gomes , Pushkar Sharad Ranade , Ravindranath Vithal Mahajan , Debendra Mallik , Omkar G. Karhade , Nitin A. Deshpande , Abhishek A. Sharma , Joshua Fryman , Stephen Morein , Matthew Adiletta
IPC分类号： H01L25/065 , H01L23/00 , H01L25/16 , H01L23/48 , H01L23/498 , H01L23/538 , H01L25/00
CPC分类号： H01L25/0652 , H01L24/08 , H01L24/80 , H01L25/167 , H01L23/481 , H01L23/49811 , H01L23/5386 , H01L25/50 , H01L2224/08121 , H01L25/0655 , H01L24/16 , H01L2224/16227 , H01L2224/16238 , H01L2924/1434 , H01L2924/1431 , H01L2924/3512 , H01L2924/3841 , H01L2224/08137 , H01L2224/08145 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896 , H01L23/49816 , H01L23/5385
摘要： Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.

14. 发明申请

US20140244792A1 DISTRIBUTING INTELLIGENCE ACROSS NETWORKS 审中-公开
标题翻译：分布式智能交叉网络
公开(公告)号：US20140244792A1
公开(公告)日：2014-08-28
申请号：US14267461
申请日：2014-05-01
申请人： Jeffrey G. Fedders , Matthew Adiletta , Valerie J. Young
发明人： Jeffrey G. Fedders , Matthew Adiletta , Valerie J. Young
IPC分类号： H04L29/08
CPC分类号： H04L65/60 , H04L67/06 , H04L67/10 , H04L67/28 , H04L67/2823 , H04L67/2842
摘要： Methods and apparatus relating to distribution of intelligence across a network are described. In one embodiment, one or more content processors may be provided at the edge of a computer network (e.g., prior to a point where data is aggregated or routed by the network). Other embodiments are also disclosed.
摘要翻译：描述了通过网络分布智能的方法和设备。在一个实施例中，可以在计算机网络的边缘处提供一个或多个内容处理器（例如，在数据被网络聚合或路由的点之前）。还公开了其他实施例。

15. 发明申请

US20090238542A1 CAPTURING EVENT INFORMATION USING A DIGITAL VIDEO CAMERA 有权
标题翻译：使用数字视频摄像机捕获事件信息
公开(公告)号：US20090238542A1
公开(公告)日：2009-09-24
申请号：US12050811
申请日：2008-03-18
申请人： Matthew Adiletta , Chengda Yang
发明人： Matthew Adiletta , Chengda Yang
IPC分类号： H04N5/00
CPC分类号： H04N5/145 , G08B13/19606 , G08B13/19663 , G08B13/19682 , H04N5/77 , H04N5/782 , H04N7/181 , H04N7/188
摘要： An event aware video system (EAVS) is to capture video frames during a first time period and process event portion of the video frames before transferring the processed data to a central computing system. The EAVS may establish a present no-event frame from the video frames, wherein a last frame of the video frames is marked as the present no-event frame if the difference between adjacent pair of frames of the video frames is less than a threshold value. The EVAS may establish an event frame, wherein a present frame captured after establishing the no-event frame is marked as the event frame if the difference between the present frame and a previous frame captured prior to the present frame is greater than the threshold value. The EAVS may generate the processed data by processing the event of the event frame.
摘要翻译：事件感知视频系统（EAVS）是在将处理后的数据传送到中央计算系统之前，在第一时间段内捕获视频帧和视频帧的处理事件部分。 EAVS可以建立来自视频帧的当前无事件帧，其中如果视频帧的相邻帧对之间的差小于阈值，则视频帧的最后一帧被标记为当前无事件帧。 EVAS可以建立事件帧，其中如果当前帧与在当前帧之前捕获的先前帧之间的差异大于阈值，则在建立无事件帧之后捕获的当前帧被标记为事件帧。 EAVS可以通过处理事件帧的事件来生成处理的数据。

16. 发明申请

US20070234009A1 Processor having a dedicated hash unit integrated within 失效
标题翻译：具有集成在其中的专用散列单元的处理器
公开(公告)号：US20070234009A1
公开(公告)日：2007-10-04
申请号：US11758892
申请日：2007-06-06
申请人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
发明人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
IPC分类号： G06F9/40
CPC分类号： G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还公开了基于执行上下文的切换和分支的指令。

17. 发明申请

US20060125663A1 Method and apparatus for implementing a bi-endian capable compiler 失效
公开(公告)号：US20060125663A1
公开(公告)日：2006-06-15
申请号：US11010490
申请日：2004-12-13
申请人： Matthew Adiletta , Hugh Wilkinson , Robert Kushlis
发明人： Matthew Adiletta , Hugh Wilkinson , Robert Kushlis
IPC分类号： H03M7/34
CPC分类号： G06F8/436 , G06F8/447 , G06F8/52
摘要： A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.

18. 发明申请

US20060112206A1 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US20060112206A1
公开(公告)日：2006-05-25
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
IPC分类号： G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

19. 发明申请

US20060090039A1 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US20060090039A1
公开(公告)日：2006-04-27
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

20. 发明申请

US20060069882A1 Memory controller for processor having multiple programmable units 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US20060069882A1
公开(公告)日：2006-03-30
申请号：US11232566
申请日：2005-09-21
申请人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
发明人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F13/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。所述处理器还包括存储器控制系统，所述存储器控制系统具有第一存储器控制器，所述第一存储器控制器基于所述存储器引用是针对偶数存储体还是存储器的奇数存储器排序存储器引用;以及第二存储器控制器，内存引用是读取引用或写入引用。

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