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11. 发明授权

US07476920B2 6F2 access transistor arrangement and semiconductor memory device 有权
标题翻译： 6F2存取晶体管布置和半导体存储器件
公开(公告)号：US07476920B2
公开(公告)日：2009-01-13
申请号：US11011040
申请日：2004-12-15
申请人： Till Schloesser
发明人： Till Schloesser
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/0207 , H01L21/76232 , H01L27/10873 , H01L27/10888 , H01L27/10897
摘要： An access transistor arrangement is provided for a 6F2 stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each pair of access transistors is separated from the adjacent pair of access transistors by an isolation transistor which is permanently turned off. The access transistors and the isolation transistors are formed as identical recessed channel transistors with elongated channel and enhanced isolation properties. The same dopant concentration may be provided for both junctions of the access transistors. As identical devices are provided both as access transistor and as isolation transistors, the complexity of lithographic patterning processes is reduced.
摘要翻译：为具有共享位线触点的6F2堆叠电容器DRAM存储单元布局提供存取晶体管布置。存取晶体管沿着半导体线成对配置。每对晶体管的两个晶体管被布置成相对于相应的公共位线部分横向反转。每对存取晶体管通过永久关闭的隔离晶体管与相邻的一对存取晶体管分离。存取晶体管和隔离晶体管形成为具有细长沟道和增强隔离性能的相同的凹槽通道晶体管。可以为存取晶体管的两个结提供相同的掺杂剂浓度。由于作为存取晶体管和隔离晶体管都提供相同的器件，因此降低了光刻图形化工艺的复杂性。

12. 发明授权

US07449739B2 Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor 失效
标题翻译：用于半导体存储单元的存储电容器和制造存储电容器的方法
公开(公告)号：US07449739B2
公开(公告)日：2008-11-11
申请号：US11339744
申请日：2006-01-25
申请人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
发明人： Johannes Heitmann , Peter Moll , Odo Wunnicke , Till Schloesser
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10852
摘要： A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.
摘要翻译：公开了用于动态半导体存储器单元的电容器，存储器和制造存储器的方法。在一个实施例中，电容器的存储电极具有衬垫形下部和杯形上部，其放置在下部的顶部。背面电极的下部包围存储电极的垫状部分。背面电极的上部被储存电极的杯状上部包围。第一电容器介质分离背面的下部和存储电极。第二电容器电介质将背面的上部和存储电极分开。电容器的电极面积被放大，而电容器电介质沉积的要求被放宽。降低沉积和蚀刻工艺的长宽比。

13. 发明申请

US20080217672A1 INTEGRATED CIRCUIT HAVING A MEMORY 审中-公开
标题翻译：具有存储器的集成电路
公开(公告)号：US20080217672A1
公开(公告)日：2008-09-11
申请号：US11684033
申请日：2007-03-09
申请人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
发明人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
IPC分类号： H01G4/40 , H01L21/62 , H01L27/01
CPC分类号： H01L27/10817 , H01G4/38 , H01G4/40 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10888 , H01L28/91
摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.
摘要翻译：公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

14. 发明申请

US20070114616A1 Field effect transistor and method of manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070114616A1
公开(公告)日：2007-05-24
申请号：US11287151
申请日：2005-11-23
申请人： Dirk Manger , Till Schloesser
发明人： Dirk Manger , Till Schloesser
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/2815 , H01L27/10873 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.
摘要翻译：布置在半导体器件中的场效应晶体管包括第一和第二掺杂源极/漏极区域，两个区域布置在栅电极的任一侧上的半导体衬底内，以及形成在衬底内的沟道区域在所述栅电极下方的掺杂源/漏区两者。在半导体衬底上形成栅氧化层。栅极电极接触栅极氧化物层的表面，并且还包括至少第一和第二导电层，其中第一和第二导电层由相对于彼此具有不同功函数的材料制成。第一导电层在表面的第一部分内接触栅极氧化物层，并且第二导电层在表面的第二部分内接触栅极氧化物层。第一导电层进一步导电连接到第二导电层。

15. 发明申请

US20070075361A1 Method for producing a trench transistor and trench transistor 失效
标题翻译：沟槽晶体管和沟槽晶体管的制造方法
公开(公告)号：US20070075361A1
公开(公告)日：2007-04-05
申请号：US11529446
申请日：2006-09-28
申请人： Richard Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
发明人： Richard Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/26586 , H01L29/66537 , H01L29/66621 , H01L29/7834
摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.
摘要翻译：在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

16. 发明授权

US07141845B2 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US07141845B2
公开(公告)日：2006-11-28
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

17. 发明申请

US20060076602A1 Dram cell pair and dram memory cell array 失效
标题翻译：戏剧单元对和阵容记忆体单元阵列
公开(公告)号：US20060076602A1
公开(公告)日：2006-04-13
申请号：US11222273
申请日：2005-09-08
申请人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Schwerin , Till Schloesser , Rolf Weis
发明人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Schwerin , Till Schloesser , Rolf Weis
IPC分类号： H01L29/94 , H01L21/8244
CPC分类号： H01L27/108 , G11C11/404 , H01L27/0207 , H01L27/10808 , H01L27/10829 , H01L29/785
摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.
摘要翻译：堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

18. 发明申请

US20060056228A1 Transistor, memory cell array and method of manufacturing a transistor 有权
标题翻译：晶体管，存储单元阵列及制造晶体管的方法
公开(公告)号：US20060056228A1
公开(公告)日：2006-03-16
申请号：US10939255
申请日：2004-09-10
申请人： Till Schloesser , Rolf Weis , Ulrike Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Schwerin
IPC分类号： G11C11/24 , H01L29/94
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

19. 发明授权

US06932916B2 Semiconductor substrate with trenches of varying depth 失效
标题翻译：具有不同深度的沟槽的半导体衬底
公开(公告)号：US06932916B2
公开(公告)日：2005-08-23
申请号：US10425179
申请日：2003-04-29
申请人： Dirk Manger , Hans-Peter Moll , Till Schloesser
发明人： Dirk Manger , Hans-Peter Moll , Till Schloesser
IPC分类号： H01L21/308 , H01L21/334 , H01L21/762 , H01L21/8242 , B44C1/22 , H01L21/302
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76229 , H01L27/1087 , H01L29/66181
摘要： A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.
摘要翻译：在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。

20. 发明申请

US20050040398A1 Test structure for improved vertical memory arrays 失效
标题翻译：用于改进垂直存储器阵列的测试结构
公开(公告)号：US20050040398A1
公开(公告)日：2005-02-24
申请号：US10766902
申请日：2004-01-30
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
IPC分类号： G11C29/50 , H01L23/58
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/50 , G11C2029/5006
摘要： An integrated circuit arrangement which has vertical FET selection transistors and storage capacitors in each case of a transistor array and of an assigned memory cell array, said storage capacitors being formed vertically into the depth of a substrate in deep trenches a test structure is integrated, which enables a plurality of vertical FET selection transistors with one another by a conductive electrode material embedded in an extended deep trench With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.
摘要翻译：一种在晶体管阵列和分配的存储单元阵列的每种情况下具有垂直FET选择晶体管和存储电容器的集成电路装置，所述存储电容器垂直形成在深沟槽中的衬底的深度，测试结构被集成，通过嵌入在扩展深沟槽中的导电电极材料使得多个垂直FET选择晶体管彼此具有这种类型的测试结构，可以评估不同半导体结处的漏电流和电容的特性值，以及不同的集成电路布置的部分以及执行可靠性压力测试。

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