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11. 发明授权

US5838205A Variable-speed phase-locked loop system with on-the-fly switching and method therefor 失效
标题翻译：具有动态切换的变速锁相环系统及其方法
公开(公告)号：US5838205A
公开(公告)日：1998-11-17
申请号：US801546
申请日：1997-02-18
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/22 , H03L7/07
CPC分类号： H03L7/07
摘要： According to the preferred embodiment, a phase-locked loop system is provided that overcomes the limitations of the prior art by providing the ability to switch output frequencies without a disruption in the phase lock of the output signal. The system uses a first phase-locked loop coupled with a second phase lock-loop such that their output signals are phase aligned and a switching mechanism for switching between the first phase lock output signal and the second phase lock loop output signal. The system is thus able to switch the frequency of its output without a disruption in the phase-lock of the signal.
摘要翻译：根据优选实施例，提供了一种锁相环系统，其通过提供切换输出频率而不会在输出信号的锁相中断的能力来克服现有技术的限制。该系统使用与第二锁相环耦合的第一锁相环，使得它们的输出信号是相位对准的，以及用于在第一锁相输出信号和第二锁相环输出信号之间切换的开关机构。因此，该系统能够切换其输出的频率而不会在信号的相位锁定中中断。

12. 发明授权

US5757238A Fast locking variable frequency phase-locked loop 失效
标题翻译：快速锁定可变频率锁相环
公开(公告)号：US5757238A
公开(公告)日：1998-05-26
申请号：US699296
申请日：1996-08-19
申请人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
发明人： Frank David Ferraiolo , John Edwin Gersbach , Charles Joseph Masenas
IPC分类号： H03L7/089 , H03L7/099 , H03L7/189 , H03L7/18
CPC分类号： H03L7/0995 , H03L7/089 , H03L7/189 , H03L2207/06
摘要： According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock. Thus, the phase-locked loop can quickly achieve phase lock at the different operating frequency.
摘要翻译：根据本发明的优选实施例，提供了一种锁相环，其克服了现有技术的限制，通过促进快速锁定转换到不同的输出频率。锁相环包括以各种选定频率提供锁相环输出信号的振荡器; 反馈分配器相位比较器用于存储对应于所选择的输出频率的锁相环控制信息的存储器存储机构; 以及数字电路机构，其在转换到不同的输出频率时从存储器存储机构接收控制信息。控制信息包括对应于不同输出频率处的输出信号的最后记录的相位差的数字计数器值。在转换时，该信息直接加载到数字电路机制，减少了相位比较器操作驱动PLL锁定所需的时间和时间。因此，锁相环可以在不同的工作频率下快速实现锁相。

13. 发明授权

US06735543B2 Method and apparatus for testing, characterizing and tuning a chip interface 失效
标题翻译：用于测试，表征和调整芯片接口的方法和装置
公开(公告)号：US06735543B2
公开(公告)日：2004-05-11
申请号：US09996839
申请日：2001-11-29
申请人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
发明人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
IPC分类号： G06F1900
CPC分类号： G01R31/31813 , G01R31/318385
摘要： An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.
摘要翻译：传输芯片中的芯片间线路传输电路和接收芯片中的互补接收电路通过在两个芯片上分别产生相同的伪随机测试数据，比较数据和记录错误，提供表征芯片间接口的能力。优选地，可以在单独的线路基础上调整一个或两个芯片以通过改变阈值检测电压，信号延迟和/或驱动器功率来减少误差。接收机电路优选地包含用于对测试周期和错误进行计数的计数器，其可以针对任何特定线路或类型的错误被屏蔽。因此，根据优选实施例的可调谐和可表征的接口因此支持针对各种调谐参数设置在各个线路上准确地确定低错误率。

14. 发明授权

US06571346B1 Elastic interface for master-slave communication 有权
标题翻译：用于主从通信的弹性接口
公开(公告)号：US06571346B1
公开(公告)日：2003-05-27
申请号：US09434800
申请日：1999-11-05
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Bradley McCredie , Paul Coteus
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Bradley McCredie , Paul Coteus
IPC分类号： G06F104
CPC分类号： G06F5/06
摘要： A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (“Bus clock”) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (“Local clock”) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master. The data sets are read in their respective sequence from the latches, responsive to the Local clock, so that the holding of respective data sets for the relatively longer time intervals in multiple latches and the reading of the data in sequence increases allowable skew of the Local clock relative to the received Bus clock.
摘要翻译：公开了用于在主设备和从设备之间进行通信的方法和设备。一系列数据组和时钟信号（“总线时钟”）从主机发送到从机，其中连续组由主机以某一频率断言，每组都被断言一段时间间隔。数据和总线时钟由从机接收，包括响应于接收的总线时钟由从机捕获数据。从器件从接收的总线时钟产生一个时钟（“本地时钟”），用于在从机上进行时钟操作。所接收的数据集的序列被保持在从属序列中的锁存器序列中，每个集合被保持一段时间间隔，该时间间隔长于由主机确定该集合的特定时间间隔。响应于本地时钟，从锁存器读取它们各自的序列中的数据集，使得在多个锁存器中相对较长的时间间隔保持相应的数据集并且依次读取数据增加本地时钟相对于接收的总线时钟。

15. 发明授权

US5757297A Method and apparatus for recovering a serial data stream using a local clock 失效
标题翻译：使用本地时钟恢复串行数据流的方法和装置
公开(公告)号：US5757297A
公开(公告)日：1998-05-26
申请号：US660522
申请日：1996-06-07
申请人： Frank David Ferraiolo , Joseph Michael Hoke , Samir Kirit Patel
发明人： Frank David Ferraiolo , Joseph Michael Hoke , Samir Kirit Patel
IPC分类号： G06F13/38 , H04L7/033 , H03M9/00
CPC分类号： H04L7/0338 , G06F13/385
摘要： A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.
摘要翻译：使用与用于发送串行数据的时钟异步的本地时钟来恢复串行数据流。输入的串行数据流被数字锁相环相移或延迟，使得它可以被本地时钟可靠地采样。 DPLL对串行数据流进行采样，并采用三个边缘检测器在本地时钟的上升沿和下降沿捕捉数据。这将数据流分成两个位样本，DPLL呈现给解串器。解串器将串行数据转换为并行数据，并将接收到的数据复制回数据字节。解串器还产生用于将并行数据呈现到例如ESCON通道逻辑的接收字节时钟。

16. 发明授权

US07117126B2 Data processing system and method with dynamic idle for tunable interface calibration 失效
公开(公告)号：US07117126B2
公开(公告)日：2006-10-03
申请号：US09946217
申请日：2001-09-05
申请人： Michael Stephen Floyd , Ravi Kumar Arimilli , Daniel Mark Dreps , Frank David Ferraiolo , Kevin F. Reick
发明人： Michael Stephen Floyd , Ravi Kumar Arimilli , Daniel Mark Dreps , Frank David Ferraiolo , Kevin F. Reick
IPC分类号： G06F11/30
CPC分类号： H04L7/02 , H04L1/24 , H04L7/0004 , H04L7/0008 , H04L7/005
摘要： A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

17. 发明授权

US07080288B2 Method and apparatus for interface failure survivability using error correction 有权
标题翻译：使用纠错的接口故障生存性的方法和装置
公开(公告)号：US07080288B2
公开(公告)日：2006-07-18
申请号：US10425423
申请日：2003-04-28
申请人： Frank David Ferraiolo , Michael Stephen Floyd , Robert James Reese , Kevin Franklin Reick
发明人： Frank David Ferraiolo , Michael Stephen Floyd , Robert James Reese , Kevin Franklin Reick
IPC分类号： G06F11/22
CPC分类号： H04L43/50 , G06F11/221 , H04L1/00 , H04L1/242
摘要： A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.
摘要翻译：一种使用错误校正的接口故障生存性的装置的方法提供当接口的位数小于或等于可用纠错深度时的接口的操作。初始化测试用于确定由于互连或电路故障导致的接口错误是否可以更正，还是禁用接口。对于任何故障的位路径，在初始化或操作空闲期间的后续对齐可被禁用。失败的位路径指示被确定并维护在硬件中，并用于绕过可能会破坏接口的后续校准。可以产生指示全部故障的故障指示并用于响应于不可校正的状况而关闭接口和/或连接的子系统并请求立即修复。可以产生指示可修正故障的第二故障指示并用于指示最终修复的需要。

18. 发明授权

US06762626B1 Phase detector 失效
标题翻译：相位检测器
公开(公告)号：US06762626B1
公开(公告)日：2004-07-13
申请号：US10422686
申请日：2003-04-24
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Gary Alan Peterson , Robert James Reese
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Gary Alan Peterson , Robert James Reese
IPC分类号： H03D900
CPC分类号： H03D13/004
摘要： A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.
摘要翻译：提供了一种与延迟锁定环结合使用的相位检测器。可编程延迟元件在接收的数据流中插入可调延迟。可编程延迟会强制输入数据的建立和保持时间。相位检测器采样逻辑检测数据窗口的标称中心与数据值窗口的设置（早期）边沿的限制以及数据有效窗口的保持时间限制（后期）边沿之间的相位差（“ 护卫队“）。在早期保护带之前到达晚于后期保护带的数据信号可能未被正确采样，并且可能说已经发生了保护带故障。状态机检测这种保护带错误并提供校正反馈信号。

19. 发明授权

US06654897B1 Dynamic wave-pipelined interface apparatus and methods therefor 有权
标题翻译：动态波形流水线接口设备及其方法
公开(公告)号：US06654897B1
公开(公告)日：2003-11-25
申请号：US09263662
申请日：1999-03-05
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
IPC分类号： G06F112
CPC分类号： G06F13/4208 , H04L7/04
摘要： An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.
摘要翻译：实现了一种用于动态波形流水线接口的装置和方法。从被发送电路接收到的数据信号在被锁存到接收装置之前经由可编程延迟装置对应于每个信号而被延迟。根据初始化过程来设置每个延迟装置中的可编程延迟，由此每个信号被偏移到最新的到达信号。此外，调整控制数据信号的锁存的输入/输出（I / O）时钟的相位，使得锁存转换基本上位于数据有效窗口的中心。

20. 发明授权

US06546530B1 Linear delay element providing linear delay steps 失效
标题翻译：线性延迟元件提供线性延迟步骤
公开(公告)号：US06546530B1
公开(公告)日：2003-04-08
申请号：US09662417
申请日：2000-09-14
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Jing Fang Hao
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Jing Fang Hao
IPC分类号： G06F1750
CPC分类号： H03K5/131 , G01R31/3016 , G01R31/3191 , G01R31/31922 , H03K5/133 , H03K2005/00058 , H03K2005/00195
摘要： A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps. In another embodiment of the present invention, a test signal is coupled to the fine delay element and to the at least one course delay element. The test signal is used to detect faults at the fine delay element and at the at least one course delay element. During the functional mode of this embodiment, power is reduced by disconnecting the test path during the functional mode.
摘要翻译：一种线性延迟线性延迟信号的方法和电路。在一个实施例中，用于线性延迟信号的集成电路中的电路包括多个控制信号。电路还包括耦合到多个控制信号中的至少一个控制信号的精细延迟元件，其中精细延迟元件包括被配置为提供对信号延迟的精细调节的逻辑电路。所述电路还包括耦合到所述精细延迟元件的至少一个线路延迟元件，其中所述至少一个线路延迟元件耦合到所述多个控制信号中的至少一个。此外，所述至少一个路线延迟元件包括逻辑电路，其被配置为向所述信号的延迟提供路线调整。用于线性延迟信号的电路被配置为提供可测试性和可编程性。用于线性延迟信号的电路被配置为提供线性延迟步骤。在本发明的另一个实施例中，测试信号耦合到精细延迟元件和至少一个线程延迟元件。测试信号用于检测精细延迟元件和至少一个行程延迟元件的故障。在本实施例的功能模式期间，在功能模式期间通过断开测试路径来降低功率。

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