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11. 发明授权

US08285789B2 Flattened butterfly processor interconnect network 有权
标题翻译：扁平蝶形处理器互联网络
公开(公告)号：US08285789B2
公开(公告)日：2012-10-09
申请号：US12195190
申请日：2008-08-20
申请人： Dennis C. Abts , John Kim , William J. Dally
发明人： Dennis C. Abts , John Kim , William J. Dally
IPC分类号： G06F15/16 , G06F15/76
CPC分类号： G06F15/17375
摘要： A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.
摘要翻译：多处理器计算机系统包括折叠蝶形处理器互连网络，折叠蝶形互连网络包括通过将每行中的路由器平坦化为每行的单个路由器，并且消除完全局部于单个路由的通道，从蝴蝶网络衍生的传统蝶形互连网络行。

12. 发明申请

US20080285562A1 FLEXIBLE ROUTING TABLES FOR A HIGH-RADIX ROUTER 有权
标题翻译：灵活的路由表用于高速路由器
公开(公告)号：US20080285562A1
公开(公告)日：2008-11-20
申请号：US12107016
申请日：2008-04-21
申请人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.
摘要翻译：用于在高基数网络中路由的系统和方法。接收并检查分组以确定分组是否可以自适应路由。如果分组可以自适应地路由，则分组自适应路由，其中路由自适应地包括选择列，计算列掩码，将分组路由到列; 并根据列屏蔽选择输出端口。如果分组可以确定地路由路由，确定性地进行路由，其中路由确定性地包括访问路由表以获得输出端口并且将路由从路由表路由到输出端口。

13. 发明授权

US09069672B2 Extended fast memory access in a multiprocessor computer system 有权
标题翻译：在多处理器计算机系统中扩展快速存储器访问
公开(公告)号：US09069672B2
公开(公告)日：2015-06-30
申请号：US12483936
申请日：2009-06-12
申请人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
发明人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
IPC分类号： G06F12/08 , G06F12/10 , H04L29/08 , G06F9/38 , G06F13/40
CPC分类号： G06F15/167 , G06F9/3834 , G06F12/0813 , G06F12/1009 , G06F12/109 , G06F13/4009 , G06F2212/163 , H04L67/00
摘要： A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.
摘要翻译：多处理器计算机系统包括第一节点，用于通过从第一节点中的节点逻辑中的请求实体接收虚拟存储器地址来访问远程节点本地的存储器。第一节点从节点逻辑中接收的虚拟地址创建网络地址，其中网络地址处于比虚拟存储器地址更大的地址空间中，并且将快速存储器访问请求从第一节点发送到在网络地址。

14. 发明申请

US20140301390A1 FLEXIBLE ROUTING TABLES FOR A HIGH-RADIX ROUTER 审中-公开
标题翻译：灵活的路由表用于高速路由器
公开(公告)号：US20140301390A1
公开(公告)日：2014-10-09
申请号：US14310832
申请日：2014-06-20
申请人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Dennis C. Abts
IPC分类号： H04L12/741 , H04L12/743
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.
摘要翻译：用于在高基数网络中路由的系统和方法。接收并检查分组以确定分组是否可以自适应路由。如果分组可以自适应地路由，则分组自适应路由，其中路由自适应地包括选择列，计算列掩码，将分组路由到列; 并根据列屏蔽选择输出端口。如果分组可以确定地路由路由，确定性地进行路由，其中路由确定性地包括访问路由表以获得输出端口并且将路由从路由表路由到输出端口。

15. 发明申请

US20110010522A1 MULTIPROCESSOR COMMUNICATION PROTOCOL BRIDGE BETWEEN SCALAR AND VECTOR COMPUTE NODES 审中-公开
标题翻译：标准和矢量电脑节目之间的多媒体通信协议桥
公开(公告)号：US20110010522A1
公开(公告)日：2011-01-13
申请号：US12814118
申请日：2010-06-11
申请人： Dennis C. Abts , Peter M. Klausler , James Nowicki
发明人： Dennis C. Abts , Peter M. Klausler , James Nowicki
IPC分类号： G06F13/36 , G06F15/76 , G06F9/02
CPC分类号： G06F15/17375
摘要： A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor interconnect network and the indirect processor interconnect network.
摘要翻译：多处理器计算机系统包括通过直接处理器互连网络耦合的多个处理器节点和由间接处理器互连网络耦合的多个处理器节点。桥接器直接耦合直接处理器互连网络和间接处理器互连网络。

16. 发明申请

US20100318747A1 ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING 失效
标题翻译： ATOMIC MEMORY OPERATION CACHE COMPOROCO WITH OPPORTUNISTIC COMBINING
公开(公告)号：US20100318747A1
公开(公告)日：2010-12-16
申请号：US12484165
申请日：2009-06-12
申请人： Dennis C. Abts , Steven L. Scott
发明人： Dennis C. Abts , Steven L. Scott
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/526 , G06F12/0815
摘要： An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.
摘要翻译：原子存储器操作高速缓存包括用于缓存原子存储器操作数据的高速缓存存储器，写入定时器和高速缓存控制器。高速缓存控制器可操作以在写定时器期满时，用存储在高速缓存存储器中的一个或多个脏原子存储器操作高速缓存条目来更新主存储器，并且还可操作以用存储的一个或多个脏原子存储器操作高速缓存条目来更新主存储器在从高速缓存存储器中消除一个或多个脏原子存储器操作高速缓存条目之后的缓存存储器中。

17. 发明授权

US07852836B2 Reduced arbitration routing system and method 有权
标题翻译：减少仲裁路由系统和方法
公开(公告)号：US07852836B2
公开(公告)日：2010-12-14
申请号：US11932413
申请日：2007-10-31
申请人： Steven L. Scott , Dennis C. Abts , Gregory Hubbard
发明人： Steven L. Scott , Dennis C. Abts , Gregory Hubbard
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , G06F11/0724 , G06F11/0781 , H04L45/40 , H04L45/54 , H04L45/60 , H04L45/742
摘要： A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.
摘要翻译：一种用于在具有由网络连接的多个节点的系统中将分组从一个节点路由到另一个节点的系统和方法。在每个节点中提供节点路由器，其中节点路由器包括多个网络端口，包括第一和第二网络端口，其中每个网络端口包括用于与其他网络节点之一通信的通信信道，多个虚拟通道输入缓冲器和多个虚拟通道暂存缓冲器，其中每个虚拟通道分段缓冲器从多个输入缓冲器之一接收数据。

18. 发明申请

US20080304491A1 RELIABLE MESSAGE TRANSPORT NETWORK 有权
标题翻译：可靠的信息传输网络
公开(公告)号：US20080304491A1
公开(公告)日：2008-12-11
申请号：US11759748
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28
CPC分类号： H04L49/90 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/188 , H04L2001/0096
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。所述发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，以维护包括所发送的分组的所述发送方中的消息缓冲器条目，以跟踪已经接收到发送分组的来自所述接收机的确认; 以保持指示从消息数据发送起的时间的定时器，并且重新发送在定时器达到超时状态时未被确认的分组。接收处理器节点可操作以向接收到分组的发送方发送确认，以使用接收到的消息表来跟踪分组，以跟踪已经接收了包含消息的一部分的分组以及消息中的所有分组是否已被接收，并且一旦接收到消息中的所有分组以重新组合接收到的消息，则处理分组。

19. 发明授权

US08792512B2 Reliable message transport network 有权
标题翻译：可靠的消息传输网络
公开(公告)号：US08792512B2
公开(公告)日：2014-07-29
申请号：US11759748
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/188 , H04L2001/0096
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。所述发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，以维护包括所发送的分组的所述发送方中的消息缓冲器条目，以跟踪已经接收到发送分组的来自所述接收机的确认; 以保持指示从消息数据发送起的时间的定时器，并且重新发送在定时器达到超时状态时未被确认的分组。接收处理器节点可操作以向接收到分组的发送方发送确认，以使用接收到的消息表来跟踪分组，以跟踪已经接收了包含消息的一部分的分组以及消息中的所有分组是否已被接收，并且一旦接收到消息中的所有分组以重新组合接收到的消息，则处理分组。

20. 发明授权

US08184626B2 High-radix interprocessor communications system and method 有权
标题翻译：高基处理器通信系统及方法
公开(公告)号：US08184626B2
公开(公告)日：2012-05-22
申请号：US12352443
申请日：2009-01-12
申请人： Steven L. Scott , Dennis C. Abts , William J. Dally
发明人： Steven L. Scott , Dennis C. Abts , William J. Dally
IPC分类号： H04L12/50
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n x p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.
摘要翻译：具有多个处理器节点，多个第一路由器和多个第二路由器的高基数处理器通信系统和方法。每个第一路由器连接到处理器节点和两个或更多个第二路由器。每个第一路由器包括输入端口，输出端口，行总线，列通道和以n×p矩阵排列的多个子开关。每行总线从多个输入端口之一接收数据，并将数据分配给多个子开关中的两个或多个。每列将数据从一个或多个子交换分配到一个或多个输出端口。每行行总线包括路由选择器，其中路由选择器包括路由选择表，该路由表选择每个分组的输出端口，并且通过一条行总线将分组路由到所选输出端口。

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