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11. 发明授权

US08629511B2 Mask free protection of work function material portions in wide replacement gate electrodes 有权
标题翻译：在宽的替代栅电极中，无功能保护功能材料部分
公开(公告)号：US08629511B2
公开(公告)日：2014-01-14
申请号：US13471852
申请日：2012-05-15
申请人： Charles W. Koburger, III , Marc A. Bergendahl , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Charles W. Koburger, III , Marc A. Bergendahl , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L27/088
CPC分类号： H01L29/401 , E21B43/305 , E21B47/122 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211
摘要： In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
摘要翻译：在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

12. 发明申请

US20130207270A1 DUAL-METAL SELF-ALIGNED WIRES AND VIAS 有权
标题翻译：双金属自对准线和VIAS
公开(公告)号：US20130207270A1
公开(公告)日：2013-08-15
申请号：US13371493
申请日：2012-02-13
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/49
CPC分类号： H01L23/485 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
摘要翻译：形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

13. 发明申请

US20130026635A1 Hybrid Copper Interconnect Structure and Method of Fabricating Same 有权
标题翻译：混合铜互连结构及其制造方法
公开(公告)号：US20130026635A1
公开(公告)日：2013-01-31
申请号：US13191999
申请日：2011-07-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater).
摘要翻译：提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜地区。根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。可以利用具有低杂质水平（即小于20ppm）的铜区域和铜回流的物理气相沉积与电镀另一个具有高杂质水平的铜区域的组合来实现含有不同杂质水平的铜区域即100ppm以上）。

14. 发明授权

US08299625B2 Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权
标题翻译：无边界互连线结构自对准到上层和下层接触孔
公开(公告)号：US08299625B2
公开(公告)日：2012-10-30
申请号：US12899911
申请日：2010-10-07
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

15. 发明申请

US20120068346A1 STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME 有权
标题翻译：用于纳米尺度金属化的结构及其制造方法
公开(公告)号：US20120068346A1
公开(公告)日：2012-03-22
申请号：US12885665
申请日：2010-09-20
申请人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
发明人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

16. 发明申请

US20130181261A1 BORDERLESS CONTACT STRUCTURE 有权
标题翻译：无边界接触结构
公开(公告)号：US20130181261A1
公开(公告)日：2013-07-18
申请号：US13348894
申请日：2012-01-12
申请人： VEERARAGHAVAN S. BASKER , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： VEERARAGHAVAN S. BASKER , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L29/78 , H01L21/28 , H01L21/20
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.
摘要翻译：公开了无边界接触结构或部分无边界接触结构和制造方法。该方法包括在栅极结构内形成栅极结构和由间隔物限定的空间。该方法还包括在该空间中，在栅极结构上和半导体材料上覆盖密封材料。该方法还包括从栅极结构和半导体材料上方移除密封材料，将密封材料留在空间内。该方法还包括在栅极结构上形成层间电介质材料。该方法进一步包括图案化层间电介质材料以形成暴露半导体材料和栅极结构的一部分的开口。该方法还包括在形成在层间电介质材料中的开口中形成接触。

17. 发明授权

US08349674B2 Forming borderless contact for transistors in a replacement metal gate process 有权
标题翻译：在替代金属栅极工艺中形成晶体管的无边界接触
公开(公告)号：US08349674B2
公开(公告)日：2013-01-08
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供了形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

18. 发明申请

US20120329275A1 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
公开(公告)号：US20120329275A1
公开(公告)日：2012-12-27
申请号：US13607677
申请日：2012-09-08
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

19. 发明申请

US20120248508A1 FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS 有权
标题翻译：在替代金属门过程中形成晶体管的无边界接触
公开(公告)号：US20120248508A1
公开(公告)日：2012-10-04
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供一种形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

20. 发明申请

US20120187566A1 AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION 有权
标题翻译：空气介质用于分层蚀刻线和通过金属化
公开(公告)号：US20120187566A1
公开(公告)日：2012-07-26
申请号：US13013108
申请日：2011-01-25
申请人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译：公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

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